[PATCH] D130560: [RISCV] Handle register spill in branch relaxation

[Piggy via Phabricator via llvm-commits]

piggynl updated this revision to Diff 450486.
piggynl added a comment.

- Revise according to @StephenFan's comments.

- Fix coding style via clang-tidy.

- Move comments about calculating ScavSlotsNum closer to their codes.

- Move tests `relax_spill` in `branch-relaxation-spill-{32,64}.ll` to `relax_jal_spill_{32,64}{,_adjust_spill_slot}` in `branch-relaxation.ll`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130560/new/

https://reviews.llvm.org/D130560

Files:
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
  llvm/test/CodeGen/RISCV/branch-relaxation.ll

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