[PATCH] D131252: [AMDGPU] Remove unused MIMG tablegen variants

[Mirko Brkusanin via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG19bb535ed994: [AMDGPU] Remove unused MIMG tablegen variants (authored by mbrkusanin).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131252/new/

https://reviews.llvm.org/D131252

Files:
  llvm/lib/Target/AMDGPU/MIMGInstructions.td


Index: llvm/lib/Target/AMDGPU/MIMGInstructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/MIMGInstructions.td
+++ llvm/lib/Target/AMDGPU/MIMGInstructions.td
@@ -981,15 +981,19 @@
   int Max = !if(!empty(!tail(range)), Min, !head(!tail(range)));
 }
 
-class MIMG_Sampler_AddrSizes<AMDGPUSampleVariant sample> {
+class MIMG_Sampler_AddrSizes<AMDGPUSampleVariant sample, bit isG16> {
   // List of all possible numbers of address words, taking all combinations of
   // A16 and image dimension into account (note: no MSAA, since this is for
   // sample/gather ops).
   list<int> AllNumAddrWords =
     !foreach(dw, !if(sample.Gradients,
-                     !if(!eq(sample.LodOrClamp, ""),
-                         [2, 3, 4, 5, 6, 7, 8, 9],
-                         [2, 3, 4, 5, 6, 7, 8, 9, 10]),
+                     !if(isG16,
+                         !if(!eq(sample.LodOrClamp, ""),
+                             [2, 3, 4, 5, 6, 7],
+                             [2, 3, 4, 5, 6, 7, 8]),
+                         !if(!eq(sample.LodOrClamp, ""),
+                             [2, 3, 4, 5, 6, 7, 8, 9],
+                             [2, 3, 4, 5, 6, 7, 8, 9, 10])),
                      !if(!eq(sample.LodOrClamp, ""),
                          [1, 2, 3],
                          [1, 2, 3, 4])),
@@ -1028,8 +1032,8 @@
 multiclass MIMG_Sampler_Src_Helper <mimgopc op, string asm,
                                     AMDGPUSampleVariant sample, RegisterClass dst_rc,
                                     bit enableDisasm = 0,
-                                    bit ExtendedImageInst = 1> {
-  foreach addr = MIMG_Sampler_AddrSizes<sample>.MachineInstrs in {
+                                    bit ExtendedImageInst = 1, bit isG16 = 0> {
+  foreach addr = MIMG_Sampler_AddrSizes<sample, isG16>.MachineInstrs in {
     let VAddrDwords = addr.NumWords in {
       if op.HAS_GFX10M then {
         def _V # addr.NumWords
@@ -1051,7 +1055,7 @@
     }
   }
 
-  foreach addr = MIMG_Sampler_AddrSizes<sample>.NSAInstrs in {
+  foreach addr = MIMG_Sampler_AddrSizes<sample, isG16>.NSAInstrs in {
     let VAddrDwords = addr.NumWords in {
       if op.HAS_GFX10M then {
         def _V # addr.NumWords # _nsa_gfx10
@@ -1087,15 +1091,15 @@
   let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), WQM = wqm,
       mayLoad = !not(isGetLod) in {
     let VDataDwords = 1 in
-    defm _V1 : MIMG_Sampler_Src_Helper<op, asm, sample, VGPR_32, 1, ExtendedImageInst>;
+    defm _V1 : MIMG_Sampler_Src_Helper<op, asm, sample, VGPR_32, 1, ExtendedImageInst, isG16>;
     let VDataDwords = 2 in
-    defm _V2 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_64, 0, ExtendedImageInst>;
+    defm _V2 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_64, 0, ExtendedImageInst, isG16>;
     let VDataDwords = 3 in
-    defm _V3 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_96, 0, ExtendedImageInst>;
+    defm _V3 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_96, 0, ExtendedImageInst, isG16>;
     let VDataDwords = 4 in
-    defm _V4 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_128, 0, ExtendedImageInst>;
+    defm _V4 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_128, 0, ExtendedImageInst, isG16>;
     let VDataDwords = 5 in
-    defm _V5 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_160, 0, ExtendedImageInst>;
+    defm _V5 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_160, 0, ExtendedImageInst, isG16>;
   }
 }
 


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