[PATCH] D131028: [AArch64] Fix cost model for FADD vector reduction

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

> Yeah this is an unfortunate potential impact on the SLP vectorizer :(
>
> I doubt the improved costs here should make things *much* worse in practice and we already have the same issue with integer `add` reduction and `mla` IIUC.  Should any negative impact materialize, I think we should work around an SLP issue in the SLPVectorizer directly, rather than through artificially inflating costs in TTI.
>
> It might also increase the incentives to properly addressing the issue :)
>
> The motivating use case for those improvements is using more accurate costs in other passes, like D131125 <https://reviews.llvm.org/D131125>

Yeah - I worry that this might come up quite a lot. Adding floats together is pretty common, and multiplying them beforehand seems just as prevalent. I have this example, although it's maybe a little odd due to the extra shuffling in the loop: https://godbolt.org/z/3oqT1b58f.


Repository:
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  https://reviews.llvm.org/D131028/new/

https://reviews.llvm.org/D131028