[PATCH] D131208: [RISCV] Prevent constant hoisting for (ashr (add (shl X, 32), C<<32), 32).

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 450218.
craig.topper added a comment.

Explicitly check the opcode of Inst in isShiftedADDWOrSUBW. This can get called with Opcode
being Instruction::Add, but the instruction being a GEP.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131208/new/

https://reviews.llvm.org/D131208

Files:
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
  llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll

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