[PATCH] D131208: [RISCV] Prevent constant hoisting for (ashr (add (shl X, 32), C<<32), 32).

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp:42
 
+// Recognize (ashr (add (shl X, 32), C << 32), 32) which DAGCombine can turn
+// into (addw X, C). If we hoist the constant, DAGCombine can't see the pattern.
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ributzka wrote:
> Is this DAGCombine RISCV specific or a generic combine?
It's RISC-V specific. See https://reviews.llvm.org/D128869


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131208/new/

https://reviews.llvm.org/D131208