[PATCH] D131047: [AArch64] Add a tablegen pattern for aarch64.neon.pmull64

[Mingming Liu via Phabricator via llvm-commits]

mingmingl created this revision.
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Let aarch64.neon.pmull64 to use higher half of the register when only
one (of two) operand is in the higher half.

- The other non higher-half operand should be in SIMD registers regardless of this tablegen pattern. Dup it to the right lane rather than fmov higher half operand operand to the lower half.

This is at least a tie, and in most cases a win, say source code execute
{pmull2, pmull} on both higher and lower half of the same source operand
respectively.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D131047

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/aarch64-pmull2.ll
  llvm/test/CodeGen/AArch64/pmull-ldr-merge.ll

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