[PATCH] D130397: [RISCV] Custom type legalize i32 loads by sign extending.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D130397#3694200 <https://reviews.llvm.org/D130397#3694200>, @asb wrote:

> Yes, from a quick check the overall impact is positive (550 files changed, 9764 insertions(+), 9810 deletions(-) - that's across rv64imafdc {lp64,lp64d} {O0,O1 <https://reviews.llvm.org/owners/package/1/>,O2 <https://reviews.llvm.org/owners/package/2/>,O3 <https://reviews.llvm.org/owners/package/3/>,Os,Oz}. But there are some cases, e.g. var-arg-24.s where some LWU get converted to LW + SLLI + SRLI.
>
> Some cases where LWU + SRLI => LW + SRLIW which I suppose might have a tiny code-size impact. LWU is never compressible, SRLI may be. LW may be compressible, SRLIW never is. Doesn't feel like a big deal either way.

Thanks Alex! I was going took at adding a DAG combine to turn sextload+and into zextload which might fix the LW + SLLI + SRLI case and maybe the LW+SRLIW cases.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130397/new/

https://reviews.llvm.org/D130397