[PATCH] D130938: [RISCV] Add scheduler class to PseudoReadVLENB.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 1 13:56:50 PDT 2022
craig.topper created this revision.
craig.topper added reviewers: kito-cheng, frasercrmck, monkchiang, nitinjohnraj, reames.
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Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D130938
Files:
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVScheduleV.td
Index: llvm/lib/Target/RISCV/RISCVScheduleV.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -9,6 +9,9 @@
//===----------------------------------------------------------------------===//
/// Define scheduler resources associated with def operands.
+// 3.6 Vector Byte Length vlenb
+def WriteRdVLENB : SchedWrite;
+
// 7. Vector Loads and Stores
// 7.4. Vector Unit-Stride Instructions
def WriteVLDE8 : SchedWrite;
@@ -493,6 +496,9 @@
multiclass UnsupportedSchedV {
let Unsupported = true in {
+// 3.6 Vector Byte Length vlenb
+def : WriteRes<WriteRdVLENB, []>;
+
// 7. Vector Loads and Stores
def : WriteRes<WriteVLDE8, []>;
def : WriteRes<WriteVLDE16, []>;
Index: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -4332,7 +4332,8 @@
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1 in {
def PseudoReadVLENB : Pseudo<(outs GPR:$rd), (ins),
- [(set GPR:$rd, (riscv_read_vlenb))]>;
+ [(set GPR:$rd, (riscv_read_vlenb))]>,
+ Sched<[WriteRdVLENB]>;
}
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1,
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