[llvm] e07a815 - [RISCV] Move Pre-RA pseudo expansion from addMachineSSAOptimization to addPreRegAlloc.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-08-01T13:44:43-07:00
New Revision: e07a8155f5168fdaff9346152d7805a47cb49405

URL: https://github.com/llvm/llvm-project/commit/e07a8155f5168fdaff9346152d7805a47cb49405
DIFF: https://github.com/llvm/llvm-project/commit/e07a8155f5168fdaff9346152d7805a47cb49405.diff

LOG: [RISCV] Move Pre-RA pseudo expansion from addMachineSSAOptimization to addPreRegAlloc.

addMachineSSAOptimization is skipped for -O0, but this pass is
required for -O0.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    llvm/test/CodeGen/RISCV/O0-pipeline.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index f97b82d8fa0b..fcd525d7dd5e 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -254,10 +254,10 @@ void RISCVPassConfig::addMachineSSAOptimization() {
 
   if (TM->getTargetTriple().getArch() == Triple::riscv64)
     addPass(createRISCVSExtWRemovalPass());
-  addPass(createRISCVPreRAExpandPseudoPass());
 }
 
 void RISCVPassConfig::addPreRegAlloc() {
+  addPass(createRISCVPreRAExpandPseudoPass());
   if (TM->getOptLevel() != CodeGenOpt::None)
     addPass(createRISCVMergeBaseOffsetOptPass());
   addPass(createRISCVInsertVSETVLIPass());

diff  --git a/llvm/test/CodeGen/RISCV/O0-pipeline.ll b/llvm/test/CodeGen/RISCV/O0-pipeline.ll
index 534f2e092a32..15d1247f825b 100644
--- a/llvm/test/CodeGen/RISCV/O0-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O0-pipeline.ll
@@ -35,6 +35,7 @@
 ; CHECK-NEXT:       RISCV DAG->DAG Pattern Instruction Selection
 ; CHECK-NEXT:       Finalize ISel and expand pseudo-instructions
 ; CHECK-NEXT:       Local Stack Slot Allocation
+; CHECK-NEXT:       RISCV Pre-RA pseudo instruction expansion pass
 ; CHECK-NEXT:       RISCV Insert VSETVLI pass
 ; CHECK-NEXT:       Eliminate PHI nodes for register allocation
 ; CHECK-NEXT:       Two-Address instruction pass