[PATCH] D130769: [RISCV] Combine and remove redundant ADD/SUB instructions

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Jul 29 07:27:28 PDT 2022


craig.topper added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/jumptable.ll:237
 ; RV64I-SMALL:       # %bb.0: # %entry
-; RV64I-SMALL-NEXT:    sext.w a0, a0
-; RV64I-SMALL-NEXT:    addi a0, a0, -1
----------------
This doesn’t look correct. (sext(x) -1) is not the same as sext(x-1).

Consider x==0x000000008000000. Sext(x)-1 is 0xffffffff7fffffff. Sext(x-1) is 0x000000007fffffff.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130769/new/

https://reviews.llvm.org/D130769



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