[PATCH] D130769: [RISCV] Combine and remove redundant ADD/SUB instructions

[Elena Lepilkina via Phabricator via llvm-commits]

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Tail duplication pass can cause appearing of redundant intructions. Support the simpliest cases in separate MachineIR pass.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D130769

Files:
  llvm/lib/Target/RISCV/CMakeLists.txt
  llvm/lib/Target/RISCV/RISCV.h
  llvm/lib/Target/RISCV/RISCVAddSubCombiner.cpp
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/O3-pipeline.ll
  llvm/test/CodeGen/RISCV/add-sub-combiner.mir
  llvm/test/CodeGen/RISCV/adds-combinations.ll
  llvm/test/CodeGen/RISCV/jumptable.ll
  llvm/test/CodeGen/RISCV/sext-zext-trunc.ll

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