[llvm] 64fdcfe - [InstCombine] add tests for icmp with cast bool logic; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 29 07:25:04 PDT 2022
Author: Sanjay Patel
Date: 2022-07-29T10:24:58-04:00
New Revision: 64fdcfeb1a7336b79f07c583752ec4db7df56657
URL: https://github.com/llvm/llvm-project/commit/64fdcfeb1a7336b79f07c583752ec4db7df56657
DIFF: https://github.com/llvm/llvm-project/commit/64fdcfeb1a7336b79f07c583752ec4db7df56657.diff
LOG: [InstCombine] add tests for icmp with cast bool logic; NFC
Added:
Modified:
llvm/test/Transforms/InstCombine/icmp.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/InstCombine/icmp.ll b/llvm/test/Transforms/InstCombine/icmp.ll
index 284e5280cba3..9c73435025ed 100644
--- a/llvm/test/Transforms/InstCombine/icmp.ll
+++ b/llvm/test/Transforms/InstCombine/icmp.ll
@@ -294,8 +294,8 @@ define i1 @test16() {
define i1 @test17(i32 %x) {
; CHECK-LABEL: @test17(
-; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[X:%.*]], 3
-; CHECK-NEXT: ret i1 [[CMP]]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[X:%.*]], 3
+; CHECK-NEXT: ret i1 [[TMP1]]
;
%shl = shl i32 1, %x
%and = and i32 %shl, 8
@@ -305,8 +305,8 @@ define i1 @test17(i32 %x) {
define <2 x i1> @test17vec(<2 x i32> %x) {
; CHECK-LABEL: @test17vec(
-; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[X:%.*]], <i32 3, i32 3>
-; CHECK-NEXT: ret <2 x i1> [[CMP]]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <2 x i32> [[X:%.*]], <i32 3, i32 3>
+; CHECK-NEXT: ret <2 x i1> [[TMP1]]
;
%shl = shl <2 x i32> <i32 1, i32 1>, %x
%and = and <2 x i32> %shl, <i32 8, i32 8>
@@ -338,8 +338,8 @@ define <2 x i1> @test17a_vec(<2 x i32> %x) {
define i1 @test18_eq(i32 %x) {
; CHECK-LABEL: @test18_eq(
-; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[X:%.*]], 3
-; CHECK-NEXT: ret i1 [[CMP]]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[X:%.*]], 3
+; CHECK-NEXT: ret i1 [[TMP1]]
;
%sh = lshr i32 8, %x
%and = and i32 %sh, 1
@@ -349,8 +349,8 @@ define i1 @test18_eq(i32 %x) {
define <2 x i1> @test18_eq_vec(<2 x i32> %x) {
; CHECK-LABEL: @test18_eq_vec(
-; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[X:%.*]], <i32 3, i32 3>
-; CHECK-NEXT: ret <2 x i1> [[CMP]]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <2 x i32> [[X:%.*]], <i32 3, i32 3>
+; CHECK-NEXT: ret <2 x i1> [[TMP1]]
;
%sh = lshr <2 x i32> <i32 8, i32 8>, %x
%and = and <2 x i32> %sh, <i32 1, i32 1>
@@ -360,8 +360,8 @@ define <2 x i1> @test18_eq_vec(<2 x i32> %x) {
define i1 @test18_ne(i32 %x) {
; CHECK-LABEL: @test18_ne(
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X:%.*]], 3
-; CHECK-NEXT: ret i1 [[CMP]]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[X:%.*]], 3
+; CHECK-NEXT: ret i1 [[TMP1]]
;
%sh = lshr i32 8, %x
%and = and i32 %sh, 1
@@ -371,8 +371,8 @@ define i1 @test18_ne(i32 %x) {
define <2 x i1> @test18_ne_vec(<2 x i32> %x) {
; CHECK-LABEL: @test18_ne_vec(
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[X:%.*]], <i32 3, i32 3>
-; CHECK-NEXT: ret <2 x i1> [[CMP]]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i32> [[X:%.*]], <i32 3, i32 3>
+; CHECK-NEXT: ret <2 x i1> [[TMP1]]
;
%sh = lshr <2 x i32> <i32 8, i32 8>, %x
%and = and <2 x i32> %sh, <i32 1, i32 1>
@@ -382,8 +382,8 @@ define <2 x i1> @test18_ne_vec(<2 x i32> %x) {
define i1 @test19(i32 %x) {
; CHECK-LABEL: @test19(
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X:%.*]], 3
-; CHECK-NEXT: ret i1 [[CMP]]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[X:%.*]], 3
+; CHECK-NEXT: ret i1 [[TMP1]]
;
%shl = shl i32 1, %x
%and = and i32 %shl, 8
@@ -393,8 +393,8 @@ define i1 @test19(i32 %x) {
define <2 x i1> @test19vec(<2 x i32> %x) {
; CHECK-LABEL: @test19vec(
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[X:%.*]], <i32 3, i32 3>
-; CHECK-NEXT: ret <2 x i1> [[CMP]]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i32> [[X:%.*]], <i32 3, i32 3>
+; CHECK-NEXT: ret <2 x i1> [[TMP1]]
;
%shl = shl <2 x i32> <i32 1, i32 1>, %x
%and = and <2 x i32> %shl, <i32 8, i32 8>
@@ -414,8 +414,8 @@ define <2 x i1> @cmp_and_signbit_vec(<2 x i3> %x) {
define i1 @test20(i32 %x) {
; CHECK-LABEL: @test20(
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X:%.*]], 3
-; CHECK-NEXT: ret i1 [[CMP]]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[X:%.*]], 3
+; CHECK-NEXT: ret i1 [[TMP1]]
;
%shl = shl i32 1, %x
%and = and i32 %shl, 8
@@ -425,8 +425,8 @@ define i1 @test20(i32 %x) {
define <2 x i1> @test20vec(<2 x i32> %x) {
; CHECK-LABEL: @test20vec(
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[X:%.*]], <i32 3, i32 3>
-; CHECK-NEXT: ret <2 x i1> [[CMP]]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i32> [[X:%.*]], <i32 3, i32 3>
+; CHECK-NEXT: ret <2 x i1> [[TMP1]]
;
%shl = shl <2 x i32> <i32 1, i32 1>, %x
%and = and <2 x i32> %shl, <i32 8, i32 8>
@@ -4110,3 +4110,112 @@ define i1 @signbit_true_logic_uses_commute(i64 %x) {
%r = icmp slt i64 %and, 0
ret i1 %r
}
+
+define i1 @zext_bool_and_eq0(i1 %x, i8 %y) {
+; CHECK-LABEL: @zext_bool_and_eq0(
+; CHECK-NEXT: [[ZX:%.*]] = zext i1 [[X:%.*]] to i8
+; CHECK-NEXT: [[A:%.*]] = and i8 [[ZX]], [[Y:%.*]]
+; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[A]], 0
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %zx = zext i1 %x to i8
+ %a = and i8 %zx, %y
+ %r = icmp eq i8 %a, 0
+ ret i1 %r
+}
+
+define <2 x i1> @zext_bool_and_eq0_commute(<2 x i1> %x, <2 x i8> %p) {
+; CHECK-LABEL: @zext_bool_and_eq0_commute(
+; CHECK-NEXT: [[ZX:%.*]] = zext <2 x i1> [[X:%.*]] to <2 x i8>
+; CHECK-NEXT: [[A:%.*]] = and <2 x i8> [[ZX]], [[P:%.*]]
+; CHECK-NEXT: [[R:%.*]] = icmp eq <2 x i8> [[A]], zeroinitializer
+; CHECK-NEXT: ret <2 x i1> [[R]]
+;
+ %y = mul <2 x i8> %p, %p ; thwart complexity-based canonicalization
+ %zx = zext <2 x i1> %x to <2 x i8>
+ %a = and <2 x i8> %y, %zx
+ %r = icmp eq <2 x i8> %a, zeroinitializer
+ ret <2 x i1> %r
+}
+
+define i1 @zext_bool_and_ne0(i1 %x, i8 %y) {
+; CHECK-LABEL: @zext_bool_and_ne0(
+; CHECK-NEXT: [[ZX:%.*]] = zext i1 [[X:%.*]] to i8
+; CHECK-NEXT: [[A:%.*]] = and i8 [[ZX]], [[Y:%.*]]
+; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[A]], 0
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %zx = zext i1 %x to i8
+ %a = and i8 %zx, %y
+ %r = icmp ne i8 %a, 0
+ ret i1 %r
+}
+
+define i1 @zext_bool_and_ne1(i1 %x, i8 %y) {
+; CHECK-LABEL: @zext_bool_and_ne1(
+; CHECK-NEXT: [[ZX:%.*]] = zext i1 [[X:%.*]] to i8
+; CHECK-NEXT: [[A:%.*]] = and i8 [[ZX]], [[Y:%.*]]
+; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[A]], 1
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %zx = zext i1 %x to i8
+ %a = and i8 %zx, %y
+ %r = icmp ne i8 %a, 1
+ ret i1 %r
+}
+
+define i1 @zext_bool_or_eq0(i1 %x, i8 %y) {
+; CHECK-LABEL: @zext_bool_or_eq0(
+; CHECK-NEXT: [[ZX:%.*]] = zext i1 [[X:%.*]] to i8
+; CHECK-NEXT: [[A:%.*]] = or i8 [[ZX]], [[Y:%.*]]
+; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[A]], 0
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %zx = zext i1 %x to i8
+ %a = or i8 %zx, %y
+ %r = icmp eq i8 %a, 0
+ ret i1 %r
+}
+
+define i1 @zext_bool_and_eq0_use(i1 %x, i64 %y) {
+; CHECK-LABEL: @zext_bool_and_eq0_use(
+; CHECK-NEXT: [[ZX:%.*]] = zext i1 [[X:%.*]] to i64
+; CHECK-NEXT: call void @use_i64(i64 [[ZX]])
+; CHECK-NEXT: [[A:%.*]] = and i64 [[ZX]], [[Y:%.*]]
+; CHECK-NEXT: [[R:%.*]] = icmp eq i64 [[A]], 0
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %zx = zext i1 %x to i64
+ call void @use_i64(i64 %zx)
+ %a = and i64 %zx, %y
+ %r = icmp eq i64 %a, 0
+ ret i1 %r
+}
+
+define i1 @zext_bool_and_ne0_use(i1 %x, i64 %y) {
+; CHECK-LABEL: @zext_bool_and_ne0_use(
+; CHECK-NEXT: [[ZX:%.*]] = zext i1 [[X:%.*]] to i64
+; CHECK-NEXT: [[A:%.*]] = and i64 [[ZX]], [[Y:%.*]]
+; CHECK-NEXT: call void @use_i64(i64 [[A]])
+; CHECK-NEXT: [[R:%.*]] = icmp ne i64 [[A]], 0
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %zx = zext i1 %x to i64
+ %a = and i64 %zx, %y
+ call void @use_i64(i64 %a)
+ %r = icmp ne i64 %a, 0
+ ret i1 %r
+}
+
+define i1 @zext_notbool_and_ne0(i2 %x, i8 %y) {
+; CHECK-LABEL: @zext_notbool_and_ne0(
+; CHECK-NEXT: [[ZX:%.*]] = zext i2 [[X:%.*]] to i8
+; CHECK-NEXT: [[A:%.*]] = and i8 [[ZX]], [[Y:%.*]]
+; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[A]], 0
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %zx = zext i2 %x to i8
+ %a = and i8 %zx, %y
+ %r = icmp ne i8 %a, 0
+ ret i1 %r
+}
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