[llvm] bc2c4f6 - [X86] combineAndnp - constant fold ANDNP(C,X) -> AND(~C,X) (REAPPLIED)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 29 07:12:41 PDT 2022
Author: Simon Pilgrim
Date: 2022-07-29T15:12:26+01:00
New Revision: bc2c4f6c8555040a74dd6cc03ae6367746329b52
URL: https://github.com/llvm/llvm-project/commit/bc2c4f6c8555040a74dd6cc03ae6367746329b52
DIFF: https://github.com/llvm/llvm-project/commit/bc2c4f6c8555040a74dd6cc03ae6367746329b52.diff
LOG: [X86] combineAndnp - constant fold ANDNP(C,X) -> AND(~C,X) (REAPPLIED)
If the LHS op has a single use then using the more general AND op is likely to allow commutation, load folding, generic folds etc.
Updated version - original version rG057db2002bb3 didn't correctly account for multiple uses of the mask that might be folding "OR(AND(X,C),AND(Y,~C)) -> OR(AND(X,C),ANDNP(C,Y))" in canonicalizeBitSelect
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/combine-udiv.ll
llvm/test/CodeGen/X86/insert-into-constant-vector.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index d5b6aeaf06da0..bcb58d30335ae 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -51196,18 +51196,30 @@ static SDValue combineAndnp(SDNode *N, SelectionDAG &DAG,
// Constant Folding
APInt Undefs0, Undefs1;
SmallVector<APInt> EltBits0, EltBits1;
- if (getTargetConstantBitsFromNode(N0, EltSizeInBits, Undefs0, EltBits0) &&
- getTargetConstantBitsFromNode(N1, EltSizeInBits, Undefs1, EltBits1)) {
+ if (getTargetConstantBitsFromNode(N0, EltSizeInBits, Undefs0, EltBits0)) {
SDLoc DL(N);
- SmallVector<APInt> ResultBits;
- for (int I = 0; I != NumElts; ++I)
- ResultBits.push_back(~EltBits0[I] & EltBits1[I]);
APInt ResultUndefs = APInt::getZero(NumElts);
- return getConstVector(ResultBits, ResultUndefs, VT, DAG, DL);
- }
- // TODO: Constant fold NOT(N0) to allow us to use AND.
- // TODO: Do this in IsNOT with suitable oneuse checks?
+ if (getTargetConstantBitsFromNode(N1, EltSizeInBits, Undefs1, EltBits1)) {
+ SmallVector<APInt> ResultBits;
+ for (int I = 0; I != NumElts; ++I)
+ ResultBits.push_back(~EltBits0[I] & EltBits1[I]);
+ return getConstVector(ResultBits, ResultUndefs, VT, DAG, DL);
+ }
+
+ // Constant fold NOT(N0) to allow us to use AND.
+ // Ensure this is only performed if we can confirm that the bitcasted source
+ // has oneuse to prevent an infinite loop with canonicalizeBitSelect.
+ if (N0->hasOneUse()) {
+ SDValue BC0 = peekThroughOneUseBitcasts(N0);
+ if (BC0.getOpcode() != ISD::BITCAST) {
+ for (APInt &Elt : EltBits0)
+ Elt = ~Elt;
+ SDValue Not = getConstVector(EltBits0, ResultUndefs, VT, DAG, DL);
+ return DAG.getNode(ISD::AND, DL, VT, Not, N1);
+ }
+ }
+ }
// Attempt to recursively combine a bitmask ANDNP with shuffles.
if (VT.isVector() && (VT.getScalarSizeInBits() % 8) == 0) {
diff --git a/llvm/test/CodeGen/X86/combine-udiv.ll b/llvm/test/CodeGen/X86/combine-udiv.ll
index 8d1aff586c7c9..c609d22cda474 100644
--- a/llvm/test/CodeGen/X86/combine-udiv.ll
+++ b/llvm/test/CodeGen/X86/combine-udiv.ll
@@ -688,19 +688,18 @@ define <16 x i8> @combine_vec_udiv_nonuniform4(<16 x i8> %x) {
define <8 x i16> @pr38477(<8 x i16> %a0) {
; SSE2-LABEL: pr38477:
; SSE2: # %bb.0:
-; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [0,4957,57457,4103,16385,35545,2048,2115]
-; SSE2-NEXT: pmulhuw %xmm0, %xmm2
-; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [0,65535,65535,65535,65535,65535,65535,65535]
-; SSE2-NEXT: pandn %xmm0, %xmm1
-; SSE2-NEXT: psubw %xmm2, %xmm0
-; SSE2-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE2-NEXT: paddw %xmm2, %xmm0
-; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [65535,65535,65535,65535,65535,65535,0,65535]
-; SSE2-NEXT: pandn %xmm0, %xmm2
-; SSE2-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE2-NEXT: por %xmm2, %xmm1
-; SSE2-NEXT: por %xmm0, %xmm1
-; SSE2-NEXT: movdqa %xmm1, %xmm0
+; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [0,4957,57457,4103,16385,35545,2048,2115]
+; SSE2-NEXT: pmulhuw %xmm0, %xmm1
+; SSE2-NEXT: movdqa %xmm0, %xmm2
+; SSE2-NEXT: psubw %xmm1, %xmm2
+; SSE2-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; SSE2-NEXT: paddw %xmm1, %xmm2
+; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535,65535,65535,0,65535]
+; SSE2-NEXT: pandn %xmm2, %xmm1
+; SSE2-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE2-NEXT: por %xmm1, %xmm0
+; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: retq
;
; SSE41-LABEL: pr38477:
diff --git a/llvm/test/CodeGen/X86/insert-into-constant-vector.ll b/llvm/test/CodeGen/X86/insert-into-constant-vector.ll
index 749ca979b4915..7fc1c173ba904 100644
--- a/llvm/test/CodeGen/X86/insert-into-constant-vector.ll
+++ b/llvm/test/CodeGen/X86/insert-into-constant-vector.ll
@@ -13,17 +13,15 @@
define <16 x i8> @elt0_v16i8(i8 %x) {
; X86-SSE2-LABEL: elt0_v16i8:
; X86-SSE2: # %bb.0:
-; X86-SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; X86-SSE2-NEXT: movaps {{.*#+}} xmm0 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
-; X86-SSE2-NEXT: andnps %xmm1, %xmm0
+; X86-SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; X86-SSE2-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: retl
;
; X64-SSE2-LABEL: elt0_v16i8:
; X64-SSE2: # %bb.0:
-; X64-SSE2-NEXT: movd %edi, %xmm1
-; X64-SSE2-NEXT: movdqa {{.*#+}} xmm0 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
-; X64-SSE2-NEXT: pandn %xmm1, %xmm0
+; X64-SSE2-NEXT: movd %edi, %xmm0
+; X64-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE2-NEXT: retq
;
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