[PATCH] D130763: [AMDGPU] Account for VData size increase from tfe bit for image instructions

Fri Jul 29 05:46:41 PDT 2022

mbrkusanin added inline comments.

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Comment at: llvm/test/MC/Disassembler/AMDGPU/mimg_vi.txt:194

-# VI: image_atomic_add v5, v1, s[8:15] dmask:0x7 unorm ; encoding: [0x00,0x17,0x48,0xf0,0x01,0x05,0x02,0x00]
+# VI: image_atomic_add v[5:7], v1, s[8:15] dmask:0x7 unorm ; encoding: [0x00,0x17,0x48,0xf0,0x01,0x05,0x02,0x00]
 0x00,0x17,0x48,0xf0,0x01,0x05,0x02,0x00
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arsenm wrote:
> Why did this get an additional output register if it's not using TFE?
It is one of examples with wrong encoding for dmask. Since dmask has 3 bits enabled it will chose vgpr96. Only valid masks are 0x1 and 0x3. It does not seem to me it's worth to update disassembler for this.

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  https://reviews.llvm.org/D130763/new/

https://reviews.llvm.org/D130763