[PATCH] D130763: [AMDGPU] Account for VData size increase from tfe bit for image instructions
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 29 05:40:55 PDT 2022
arsenm added a comment.
Does TFE actually work for atomics? Do we not have any IR tests for TFE?
================
Comment at: llvm/test/MC/Disassembler/AMDGPU/mimg_vi.txt:194
-# VI: image_atomic_add v5, v1, s[8:15] dmask:0x7 unorm ; encoding: [0x00,0x17,0x48,0xf0,0x01,0x05,0x02,0x00]
+# VI: image_atomic_add v[5:7], v1, s[8:15] dmask:0x7 unorm ; encoding: [0x00,0x17,0x48,0xf0,0x01,0x05,0x02,0x00]
0x00,0x17,0x48,0xf0,0x01,0x05,0x02,0x00
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Why did this get an additional output register if it's not using TFE?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D130763/new/
https://reviews.llvm.org/D130763
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