[PATCH] D130677: [AMDGPU] Fix DGEMM hazard for GFX90a

[Austin Kerbow via Phabricator via llvm-commits]

kerbowa added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPU.td:282
 
+def FeatureDGEMMVALUWriteMemOpBug : SubtargetFeature<"dgemm-valu-write-mem-op-bug",
+  "HasDGEMMVALUWriteMemOpBug",
----------------
vangthao wrote:
> rampitec wrote:
> > I do not believe it deserves a feature bit. These bits are limited.
> Is there a way to check for gfx90a only? I thought about `hasGFX90AInsts()` but this also includes gfx940. We could exclude gfx940 with `!hasGFX940Insts()` but that does not seem like a clean way of doing so.
Isn't the max number of bits 256? So we are at 143/256? Do we have a good way of checking for a specific processor beyond adding feature bits for each one?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130677/new/

https://reviews.llvm.org/D130677