[PATCH] D130700: [AArch64][DAGCombine] Add pushSignExtendThroughExtractSubvector

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:15044-15045
+
+  if (VT.isScalableVector())
+    return SDValue();
+
----------------
Is this necessary? What are you trying to protect against?


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:15059
+
+  //    (sign_extend_inreg (extract_subvector (anyext v) Idx))
+  // => (extract_subvector (sign_extend v) Idx)
----------------
`SIGN_EXTEND_INREG` has a "type" operand that defines the size of the data being extended.  You'll need to ensure this matches the element type of data being any extended.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130700/new/

https://reviews.llvm.org/D130700