[PATCH] D77804: [DAG] Enable ISD::SRL SimplifyMultipleUseDemandedBits handling inside SimplifyDemandedBits

[Simon Pilgrim via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG69d5a038b90d: [DAG] Enable ISD::SRL SimplifyMultipleUseDemandedBits handling inside… (authored by RKSimon).

Changed prior to commit:
  https://reviews.llvm.org/D77804?vs=447979&id=448320#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77804/new/

https://reviews.llvm.org/D77804

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/AArch64/parity.ll
  llvm/test/CodeGen/AArch64/shift-accumulate.ll
  llvm/test/CodeGen/AMDGPU/bswap.ll
  llvm/test/CodeGen/AMDGPU/ds-alignment.ll
  llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
  llvm/test/CodeGen/AMDGPU/fabs.f16.ll
  llvm/test/CodeGen/AMDGPU/fshr.ll
  llvm/test/CodeGen/AMDGPU/idot4s.ll
  llvm/test/CodeGen/AMDGPU/idot4u.ll
  llvm/test/CodeGen/AMDGPU/idot8s.ll
  llvm/test/CodeGen/AMDGPU/idot8u.ll
  llvm/test/CodeGen/AMDGPU/saddsat.ll
  llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
  llvm/test/CodeGen/AMDGPU/shift-i128.ll
  llvm/test/CodeGen/AMDGPU/ssubsat.ll
  llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
  llvm/test/CodeGen/AMDGPU/trunc-combine.ll
  llvm/test/CodeGen/AMDGPU/uaddsat.ll
  llvm/test/CodeGen/AMDGPU/usubsat.ll
  llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll
  llvm/test/CodeGen/ARM/parity.ll
  llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll
  llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
  llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
  llvm/test/CodeGen/RISCV/rv64zbb-zbp-zbkb.ll
  llvm/test/CodeGen/RISCV/rv64zbb.ll
  llvm/test/CodeGen/RISCV/rv64zbp.ll
  llvm/test/CodeGen/RISCV/sextw-removal.ll
  llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll
  llvm/test/CodeGen/X86/bitreverse.ll
  llvm/test/CodeGen/X86/ctpop-combine.ll
  llvm/test/CodeGen/X86/illegal-bitfield-loadstore.ll
  llvm/test/CodeGen/X86/ins_subreg_coalesce-1.ll
  llvm/test/CodeGen/X86/load-local-v4i5.ll
  llvm/test/CodeGen/X86/masked_compressstore.ll
  llvm/test/CodeGen/X86/vector-mulfix-legalize.ll

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