[PATCH] D130560: [RISCV] Handle register spill in branch relaxation

[Piggy via Phabricator via llvm-commits]

piggynl added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:1077
+  if (!isInt<20>(EstimateFunctionSizeInBytes(MF, *TII))) {
+    int FI = MFI.CreateStackObject(RegInfo->getSpillSize(*RC),
+                                   RegInfo->getSpillAlign(*RC), false);
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StephenFan wrote:
> Actually, scavenging spill slots can be reused. But here we always create a scavenging spill slot even if there is already a scavenging spill slot.
Since branch relaxation pass is after instruction scheduling, I'm not sure whether the jump could be placed in the middle of a spill from previous pass, and the slot's content could be overwritten if we reuse the slot.

I'm not familiar with instruction scheduling, so please correct me for any mistake I made. Thank you in advance!


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  https://reviews.llvm.org/D130560/new/

https://reviews.llvm.org/D130560