[PATCH] D130047: [RISCV] Disable constant hoisting for multiply by negated power of 2.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 27 09:38:58 PDT 2022
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG9b27d1320496: [RISCV] Disable constant hoisting for multiply by negated power of 2. (authored by craig.topper).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D130047/new/
https://reviews.llvm.org/D130047
Files:
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll
Index: llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll
===================================================================
--- llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll
+++ llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll
@@ -72,3 +72,12 @@
%2 = and i64 %1, 4294967295
ret i64 %2
}
+
+; Check that we don't hoist mul with negated power of 2.
+define i64 @test9(i64 %a) nounwind {
+; CHECK-LABEL: test9
+; CHECK: mul i64 %a, -4294967296
+ %1 = mul i64 %a, -4294967296
+ %2 = mul i64 %1, -4294967296
+ ret i64 %2
+}
Index: llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -71,7 +71,13 @@
case Instruction::Add:
case Instruction::Or:
case Instruction::Xor:
+ Takes12BitImm = true;
+ break;
case Instruction::Mul:
+ // Negated power of 2 is a shift and a negate.
+ if (Imm.isNegatedPowerOf2())
+ return TTI::TCC_Free;
+ // FIXME: There is no MULI instruction.
Takes12BitImm = true;
break;
case Instruction::Sub:
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