[llvm] c0b3f7a - [DAG] SimplifyDemandedBits - ensure we clear known One bits that AssertZext asserts are really known Zero

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2022-07-27T13:57:47+01:00
New Revision: c0b3f7a50fdf22c4a6e0c5e6e3ef2147f44bf566

URL: https://github.com/llvm/llvm-project/commit/c0b3f7a50fdf22c4a6e0c5e6e3ef2147f44bf566
DIFF: https://github.com/llvm/llvm-project/commit/c0b3f7a50fdf22c4a6e0c5e6e3ef2147f44bf566.diff

LOG: [DAG] SimplifyDemandedBits - ensure we clear known One bits that AssertZext asserts are really known Zero

Matches ComputeKnownBits behaviour

Thanks to @uabelho for the fuzz regression report on D129765

Added: 
    llvm/test/CodeGen/X86/assertzext-demanded.ll

Modified: 
    llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 195c0e6a836f0..4a960c4e15b41 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -3506,7 +3506,7 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
   case ISD::AssertZext: {
     EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
     APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits());
-    Known = computeKnownBits(Op.getOperand(0), Depth+1);
+    Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
     Known.Zero |= (~InMask);
     Known.One  &= (~Known.Zero);
     break;

diff  --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 102c412fe72fc..bd471f23d512d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -2421,6 +2421,7 @@ bool TargetLowering::SimplifyDemandedBits(
     assert(!Known.hasConflict() && "Bits known to be one AND zero?");
 
     Known.Zero |= ~InMask;
+    Known.One &= (~Known.Zero);
     break;
   }
   case ISD::EXTRACT_VECTOR_ELT: {

diff  --git a/llvm/test/CodeGen/X86/assertzext-demanded.ll b/llvm/test/CodeGen/X86/assertzext-demanded.ll
new file mode 100644
index 0000000000000..3d2120578b49e
--- /dev/null
+++ b/llvm/test/CodeGen/X86/assertzext-demanded.ll
@@ -0,0 +1,39 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
+
+; Reported on D129765
+define void @simplify_assertzext(ptr %0) {
+; CHECK-LABEL: simplify_assertzext:
+; CHECK:       # %bb.0: # %BB
+; CHECK-NEXT:    movl $275047, %eax # imm = 0x43267
+; CHECK-NEXT:    movb $1, %cl
+; CHECK-NEXT:    .p2align 4, 0x90
+; CHECK-NEXT:  .LBB0_1: # %CF246
+; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    testb %cl, %cl
+; CHECK-NEXT:    jne .LBB0_1
+; CHECK-NEXT:  # %bb.2: # %CF260
+; CHECK-NEXT:    orl $278403, %eax # imm = 0x43F83
+; CHECK-NEXT:    movl %eax, (%rdi)
+; CHECK-NEXT:    .p2align 4, 0x90
+; CHECK-NEXT:  .LBB0_3: # %CF242
+; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    jmp .LBB0_3
+BB:
+  br label %CF246
+
+CF246:                                            ; preds = %CF246, %BB
+  %Sl23 = select i1 true, i32 275047, i32 355835
+  %Cmp24 = fcmp ule float 0x3841668540000000, undef
+  br i1 %Cmp24, label %CF246, label %CF260
+
+CF260:                                            ; preds = %CF246
+  %B29 = or i32 %Sl23, 278403
+  store i32 %B29, ptr %0, align 4
+  %L40 = load <4 x i1>, ptr %0, align 1
+  br label %CF242
+
+CF242:                                            ; preds = %CF242, %CF260
+  %Sl53 = select i1 undef, <4 x i1> %L40, <4 x i1> undef
+  br label %CF242
+}