[PATCH] D130621: [RISCV] Add target feature to force-enable atomics

[Nikita Popov via Phabricator via llvm-commits]

nikic added a comment.

In D130621#3681861 <https://reviews.llvm.org/D130621#3681861>, @jrtc27 wrote:

> Why atomics-32 and not something that generalises to include 64-bit atomics on RV64?

Good point. I've changed this to a `+force-atomics` feature that works for both riscv32 and riscv64. (If this patch lands, I'll also rename the ARM feature to match.)



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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoA.td:111
+let Predicates = [HasAtomicLdSt32] in {
+  defm : LdPat<atomic_load_8,  LB>;
+  defm : LdPat<atomic_load_16, LH>;
----------------
pcwang-thead wrote:
> nikic wrote:
> > jrtc27 wrote:
> > > Don’t duplicate patterns
> > What's the right way to avoid the duplication here? Is there a way to use "or" inside Predicates?
> You can define an `or` predicate in RISCV.td like `HasStdExtMOrZmmul`, `HasStdExtZfhOrZfhmin`, etc.
Thanks, I did that now!


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https://reviews.llvm.org/D130621