[PATCH] D130621: [RISCV] Add target feature to force 32-bit atomics

[Nikita Popov via Phabricator via llvm-commits]

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This adds a `+atomics-32` target feature with the same semantics as on ARM (D130480 <https://reviews.llvm.org/D130480>). For RISCV targets without the `+a` extension, this forces LLVM to assume that lock-free 32-bit atomics are available.

This means that atomic load/store are lowered to a simple load/store (and fence as necessary), as these are guaranteed to be atomic (as long as they're aligned). Atomic RMW/CAS are lowered to `__sync` (rather than `__atomic`) libcalls. Responsibility for providing the `__sync` libcalls lies with the user (for privileged single-core code they can be implemented by disabling interrupts). Code using `+atomics-32` and `-atomics-32` are not ABI compatible if atomic variables cross the ABI boundary.

This target feature will be used by Rust's riscv32i target family to support the use of atomic load/store without atomic RMW/CAS.


https://reviews.llvm.org/D130621

Files:
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoA.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/forced-atomic32.ll

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