[PATCH] D130560: [RISCV] Handle register spill in branch relaxation

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:1007
+    for (auto &MI : MBB)
+      FnSize += TII.getInstSizeInBytes(MI);
+
----------------
You might want to consider using a more conservative estimate for conditional branches, since they can be relaxed to unconditional branches.  (I know we don't do this in the ARM function you borrowed this from, but probably we should.)


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D130560/new/

https://reviews.llvm.org/D130560