[PATCH] D130367: [AMDGPU] avoid blind converting to VALU REG_SEQUENCE and PHIs

[Alexander via Phabricator via llvm-commits]

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In the we 2e29b0138ca243 <https://reviews.llvm.org/rG2e29b0138ca243c7d288622524a004c84acbbb9e> introduce specific solving algorithm

           that analyzes the VGPR to SGPR copies use chains and either lowers
  	 copy to v_readfirstlane_b32 or converts the whole chain to VALU forms.
  	 Same time we still have the code that blindly converts to VALU REG_SEQUENCE and PHIs
  	 in case they produce SGPR but have VGPRs input operands. In case the REG_SEQUENCE and PHIs
  	 are in the VGPR to SGPR copy use chain, and this chain was considered long enough to convert
  	 copy to v_readfistlane_b32, further lowering them to VALU leads to several kinds of issues.
  	 At first we have v_readfistlane_b32 that is completely useless because the most part of its use chain
  	 was moved to VALU forms. At second we may encounter a subtle bugs related to the EXEC-dependent CF
  	 because of weird mixing SALU and VALU instructions.
  	 This change removes the code that moves REG_SEQUENCE and PHIs to VALU. Instead we use the fact
  	 that both REG_SEQUENCE and PHIs have copy semantic. That is, if they define SGPR but have VGPR inputs,
  	 we insert VGPR to SGPR copies to make them pure SGPR. Then, the new copies are processed bu the common
  	 VGPR to SGPR lowering algorithm.
  	 This is the Part 2 in the series of commits aiming the massive refactoring the SIFixSGPRCopies pass.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D130367

Files:
  llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
  llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
  llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
  llvm/test/CodeGen/AMDGPU/ds_read2.ll
  llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
  llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
  llvm/test/CodeGen/AMDGPU/sdiv64.ll
  llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
  llvm/test/CodeGen/AMDGPU/spill-vgpr.ll
  llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
  llvm/test/CodeGen/AMDGPU/srem64.ll
  llvm/test/CodeGen/AMDGPU/udiv.ll
  llvm/test/CodeGen/AMDGPU/udiv64.ll
  llvm/test/CodeGen/AMDGPU/urem64.ll
  llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
  llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll

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