[PATCH] D130191: [RISCV] Teach ComputeNumSignBitsForTargetNode about Intrinsic::riscv_masked_cmpxchg_i64

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9682
+      // ANDing the result with a mask. Therefore, the sign bits are the
+      // minimum of 33 (from the LR_W) and the number of sign bits in the mask
+      // operand.
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I don't follow this comment.  Is there some documentation you can point to for what this intrinsic does?  Or a good pointer in code to understand it?

If I'm gathering this correctly, the and-by-mask is to handle the zext of the type less than XLEN?  Not following where the sign bit below that is coming from.  


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130191/new/

https://reviews.llvm.org/D130191