[PATCH] D130191: [RISCV] Teach ComputeNumSignBitsForTargetNode about Intrinsic::riscv_masked_cmpxchg_i64

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

Do we care about other masked i64 atomic intrinsics, and do the i32 ones ever see a benefit from implementing an equivalent?



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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9679
+      break;
+    case Intrinsic::riscv_masked_cmpxchg_i64:
+      // The output of the intrinsic is generated by performing an LR_W and
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Should have extra { } so it's easy to add other cases


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  https://reviews.llvm.org/D130191/new/

https://reviews.llvm.org/D130191