[llvm] 31b8939 - [RISCV] Recognize bexti from (srl (and X, 1<<C), C).

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-07-20T15:03:52-07:00
New Revision: 31b8939dede49effdca25431a108b44e8d389544

URL: https://github.com/llvm/llvm-project/commit/31b8939dede49effdca25431a108b44e8d389544
DIFF: https://github.com/llvm/llvm-project/commit/31b8939dede49effdca25431a108b44e8d389544.diff

LOG: [RISCV] Recognize bexti from (srl (and X, 1<<C), C).

This is the form we get for (zext (setne (and X 1<<C))). We only
had bexti patterns for the alternative form (and (srl X, C), 1).

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    llvm/test/CodeGen/RISCV/rv32zbs.ll
    llvm/test/CodeGen/RISCV/rv64zbs.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 88bdc5aff5acd..d5826b46d738e 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -690,6 +690,14 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
     // 32 trailing ones should use srliw via tablegen pattern.
     if (TrailingOnes == 32 || ShAmt >= TrailingOnes)
       break;
+    // If C2 is (1 << ShAmt) use bexti if possible.
+    if (Subtarget->hasStdExtZbs() && ShAmt + 1 == TrailingOnes) {
+      SDNode *BEXTI =
+          CurDAG->getMachineNode(RISCV::BEXTI, DL, VT, N0->getOperand(0),
+                                 CurDAG->getTargetConstant(ShAmt, DL, VT));
+      ReplaceNode(Node, BEXTI);
+      return;
+    }
     unsigned LShAmt = Subtarget->getXLen() - TrailingOnes;
     SDNode *SLLI =
         CurDAG->getMachineNode(RISCV::SLLI, DL, VT, N0->getOperand(0),

diff  --git a/llvm/test/CodeGen/RISCV/rv32zbs.ll b/llvm/test/CodeGen/RISCV/rv32zbs.ll
index 1d7b618bbde39..d770cb68a36b3 100644
--- a/llvm/test/CodeGen/RISCV/rv32zbs.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbs.ll
@@ -337,11 +337,16 @@ define i64 @bexti_i64(i64 %a) nounwind {
 }
 
 define signext i32 @bexti_i32_cmp(i32 signext %a) nounwind {
-; CHECK-LABEL: bexti_i32_cmp:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    slli a0, a0, 26
-; CHECK-NEXT:    srli a0, a0, 31
-; CHECK-NEXT:    ret
+; RV32I-LABEL: bexti_i32_cmp:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    slli a0, a0, 26
+; RV32I-NEXT:    srli a0, a0, 31
+; RV32I-NEXT:    ret
+;
+; RV32ZBS-LABEL: bexti_i32_cmp:
+; RV32ZBS:       # %bb.0:
+; RV32ZBS-NEXT:    bexti a0, a0, 5
+; RV32ZBS-NEXT:    ret
   %and = and i32 %a, 32
   %cmp = icmp ne i32 %and, 0
   %zext = zext i1 %cmp to i32
@@ -349,12 +354,18 @@ define signext i32 @bexti_i32_cmp(i32 signext %a) nounwind {
 }
 
 define i64 @bexti_i64_cmp(i64 %a) nounwind {
-; CHECK-LABEL: bexti_i64_cmp:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    slli a0, a0, 26
-; CHECK-NEXT:    srli a0, a0, 31
-; CHECK-NEXT:    li a1, 0
-; CHECK-NEXT:    ret
+; RV32I-LABEL: bexti_i64_cmp:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    slli a0, a0, 26
+; RV32I-NEXT:    srli a0, a0, 31
+; RV32I-NEXT:    li a1, 0
+; RV32I-NEXT:    ret
+;
+; RV32ZBS-LABEL: bexti_i64_cmp:
+; RV32ZBS:       # %bb.0:
+; RV32ZBS-NEXT:    bexti a0, a0, 5
+; RV32ZBS-NEXT:    li a1, 0
+; RV32ZBS-NEXT:    ret
   %and = and i64 %a, 32
   %cmp = icmp ne i64 %and, 0
   %zext = zext i1 %cmp to i64

diff  --git a/llvm/test/CodeGen/RISCV/rv64zbs.ll b/llvm/test/CodeGen/RISCV/rv64zbs.ll
index dce206ba0c5f1..6ccb371529647 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbs.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbs.ll
@@ -429,11 +429,16 @@ define i64 @bexti_i64(i64 %a) nounwind {
 }
 
 define signext i32 @bexti_i32_cmp(i32 signext %a) nounwind {
-; CHECK-LABEL: bexti_i32_cmp:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    slli a0, a0, 58
-; CHECK-NEXT:    srli a0, a0, 63
-; CHECK-NEXT:    ret
+; RV64I-LABEL: bexti_i32_cmp:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a0, a0, 58
+; RV64I-NEXT:    srli a0, a0, 63
+; RV64I-NEXT:    ret
+;
+; RV64ZBS-LABEL: bexti_i32_cmp:
+; RV64ZBS:       # %bb.0:
+; RV64ZBS-NEXT:    bexti a0, a0, 5
+; RV64ZBS-NEXT:    ret
   %and = and i32 %a, 32
   %cmp = icmp ne i32 %and, 0
   %zext = zext i1 %cmp to i32
@@ -441,11 +446,16 @@ define signext i32 @bexti_i32_cmp(i32 signext %a) nounwind {
 }
 
 define i64 @bexti_i64_cmp(i64 %a) nounwind {
-; CHECK-LABEL: bexti_i64_cmp:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    slli a0, a0, 58
-; CHECK-NEXT:    srli a0, a0, 63
-; CHECK-NEXT:    ret
+; RV64I-LABEL: bexti_i64_cmp:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a0, a0, 58
+; RV64I-NEXT:    srli a0, a0, 63
+; RV64I-NEXT:    ret
+;
+; RV64ZBS-LABEL: bexti_i64_cmp:
+; RV64ZBS:       # %bb.0:
+; RV64ZBS-NEXT:    bexti a0, a0, 5
+; RV64ZBS-NEXT:    ret
   %and = and i64 %a, 32
   %cmp = icmp ne i64 %and, 0
   %zext = zext i1 %cmp to i64