[PATCH] D130099: [RISCV] Optimize (br_cc (and X, 0x80000000), 0, seteq, dest) on RV64

[Philip Reames via Phabricator via llvm-commits]

reames added a comment.

In D130099#3665984 <https://reviews.llvm.org/D130099#3665984>, @craig.topper wrote:

> In D130099#3665426 <https://reviews.llvm.org/D130099#3665426>, @reames wrote:
>
>> Can't we do something more general here using shifts?
>>
>> For one bit masks, can't we shift the desired bit to one end and then test?  For a left shift, this would be moving the desired bit to test into bit 64 (sign bit) and using the signed comparison as in this patch.  For a right shift, this would be moving the desired bit into bit 0, and testing against zero.  We do have a snez I believe.
>
> Right shift doesn’t work without clearing the bits that are above the tested bit. But left shift would work.

You're right, you'd need an and 0x1 after the right shift to isolate the bit.  Might still be worth doing over materializing the large mask constant - that's at least an LUI + AND, so SRLI + AND both with immediate operands seems to be slightly better.

But yes, the ability to do the left shift and signed compare is strictly better, so we should do that one.  :)

For multiple bit masks, maybe the right shift variant is worth exploring providing the shifted bit mask fits in the immediate encoding.  So any mask with set bits separated by less than 12 bits.  I don't see a multi-bit mask variant of the left shift one off the top of my head.


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