[PATCH] D129927: [MachineScheduler] Try to issue the load instruction preferentially

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

The scheduling info will come from https://github.com/llvm/llvm-project/blob/439668871ac992159f00309d3bd837db287bdea6/llvm/lib/Target/AArch64/AArch64SchedTSV110.td#L501. It tends to assume a L1 <https://reviews.llvm.org/L1> cache latency, as setting it much high tends to push the scheduler into making worse decisions.
It may be better to be a little aggressive after post-ra. I don't know the cpu very well.


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  https://reviews.llvm.org/D129927/new/

https://reviews.llvm.org/D129927