[PATCH] D129927: [MachineScheduler] Try to issue the load instruction preferentially

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Sorry for the delay. My immediate thought was why not just increase the latency on the load. But I guess this is different. Most cpus can only issue a certain number of loads per cycle, so "load;load;load;load;load;add;add;add;add" will be worse than emitting "load;add;load;add;load;add;load;add". It will depend on the latencies of the loads though and any dependencies, most time we encode an optimistic latency into the schedule latencies for loads.

Most cpus will out-of-order execute around that anyway nowadays though, just filling up internal queues. It depends on how much they are fetching per cycle and what is acting as the bottleneck. So I wanted to run some benchmarks to see if this did modify anything, but they didn't show much change.

Umm. Is this for a downstream cpu or is it using tsv110? Does the scheduling model have the correct information for the loads in question? I worry that some of this code we are adding looks like dead code that someone could rightly delete as unused. Should they be added to the tuning features for the tsv110 cpu?


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https://reviews.llvm.org/D129927