[PATCH] D129726: [InstCombine] (ShiftValC >> Y) >s -1/<s 0 --> Y != 0/==0

[Chenbing.Zheng via Phabricator via llvm-commits]

Chenbing.Zheng updated this revision to Diff 446070.
Chenbing.Zheng retitled this revision from "[InstCombine] (ShiftValC >> Y) >s -1 --> Y != 0 with ShiftValC < 0" to "[InstCombine] (ShiftValC >> Y) >s -1/<s 0 --> Y != 0/==0 ".
Chenbing.Zheng edited the summary of this revision.
Chenbing.Zheng added a comment.

address comments


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129726/new/

https://reviews.llvm.org/D129726

Files:
  llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
  llvm/test/Transforms/InstCombine/icmp-shr.ll

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