[PATCH] D130106: [LV] Fix miscompile due to srem/sdiv speculation safety condition

[Philip Reames via Phabricator via llvm-commits]

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An srem or sdiv has two cases which can cause undefined behavior, not just one.  The existing code did not account for this, and as a result, we miscompiled when we encountered e.g. a srem i64 %v, -1 in a conditional block.

Instead of hand rolling the logic, just use the utility function which exists exactly for this purpose.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D130106

Files:
  llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
  llvm/test/Transforms/LoopVectorize/RISCV/scalable-divrem.ll

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