[PATCH] D130099: [RISCV] Optimize (br_cc (and X, 0x80000000), 0, seteq, dest) on RV64

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Jul 19 09:44:54 PDT 2022


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The 0x80000000 would normally require constant materialization, but
we can replace it with a sext.w to copy bit 31 to bit 63 and use a
sign compare with 0 to test the bit.

We can do something similar for setne and for select_cc which will
eventually becomes a branch. The setne case for select_cc becomes
an srliw instead through other means and I'm not sure it's worth
changing.

I chose sext.w because it's one instruction, srliw would need a
srl+and to be emitted. And a sext.w might be foldable into an earlier
instruction.

We don't want to do this for setcc that won't become a branch because
we don't have a sgez instruction. For those an srliw and an xori is
going to be better. That's probably best done from an isel pattern so
we don't expand and+setcc to srl+and+xor in the DAG.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D130099

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/i64-icmp.ll

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