[PATCH] D130075: [InstCombine] Try not to demand low order bits for Add

[Jay Foad via Phabricator via llvm-commits]

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Don't demand low order bits from the LHS of an Add if:

- they are not demanded in the result, and
- they are known to be zero in the RHS, so they can't possibly overflow and affect higher bit positions

This is intended to avoid a regression from a future patch to change
the order of canonicalization of ADD and AND.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D130075

Files:
  llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
  llvm/test/Transforms/LoopVectorize/X86/float-induction-x86.ll

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