[llvm] 3fcaea1 - [RISCV][test] Precommit test for D122791.
via llvm-commits
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Mon Jul 18 20:09:33 PDT 2022
Author: jacquesguan
Date: 2022-07-19T10:56:02+08:00
New Revision: 3fcaea176cbf54a5ebd111296ba563f350c3923f
URL: https://github.com/llvm/llvm-project/commit/3fcaea176cbf54a5ebd111296ba563f350c3923f
DIFF: https://github.com/llvm/llvm-project/commit/3fcaea176cbf54a5ebd111296ba563f350c3923f.diff
LOG: [RISCV][test] Precommit test for D122791.
Differential Revision: https://reviews.llvm.org/D123362
Added:
Modified:
llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
index 0aa82ca91394b..ec5267694a8ed 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
@@ -860,3 +860,33 @@ define <vscale x 8 x i64> @vadd_vx_nxv8i64_1(<vscale x 8 x i64> %va) {
%vc = add <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i64> %vc
}
+
+define <vscale x 8 x i64> @vadd_xx_nxv8i64(i64 %a, i64 %b) nounwind {
+; RV32-LABEL: vadd_xx_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV32-NEXT: vlse64.v v8, (a0), zero
+; RV32-NEXT: sw a3, 12(sp)
+; RV32-NEXT: sw a2, 8(sp)
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vadd.vv v8, v8, v16
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vadd_xx_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
+; RV64-NEXT: vmv.v.x v8, a0
+; RV64-NEXT: vadd.vx v8, v8, a1
+; RV64-NEXT: ret
+ %head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
+ %splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
+ %head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
+ %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
+ %v = add <vscale x 8 x i64> %splat1, %splat2
+ ret <vscale x 8 x i64> %v
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
index 7f7c099576e00..52b1e69988297 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
@@ -1352,3 +1352,32 @@ define <vscale x 8 x i64> @vand_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
ret <vscale x 8 x i64> %vc
}
+define <vscale x 8 x i64> @vand_xx_nxv8i64(i64 %a, i64 %b) nounwind {
+; RV32-LABEL: vand_xx_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV32-NEXT: vlse64.v v8, (a0), zero
+; RV32-NEXT: sw a3, 12(sp)
+; RV32-NEXT: sw a2, 8(sp)
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vand.vv v8, v8, v16
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vand_xx_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
+; RV64-NEXT: vmv.v.x v8, a0
+; RV64-NEXT: vand.vx v8, v8, a1
+; RV64-NEXT: ret
+ %head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
+ %splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
+ %head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
+ %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
+ %v = and <vscale x 8 x i64> %splat1, %splat2
+ ret <vscale x 8 x i64> %v
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
index b1e067b0d1e84..bcbf8bafc7374 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
@@ -2,6 +2,9 @@
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
+; RUN: llc -mtriple=riscv32 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
+
define <vscale x 1 x i8> @vmul_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
; CHECK-LABEL: vmul_vv_nxv1i8:
; CHECK: # %bb.0:
@@ -919,3 +922,33 @@ define <vscale x 8 x i64> @vmul_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
%vc = mul <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i64> %vc
}
+
+define <vscale x 8 x i64> @vmul_xx_nxv8i64(i64 %a, i64 %b) nounwind {
+; RV32-LABEL: vmul_xx_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV32-NEXT: vlse64.v v8, (a0), zero
+; RV32-NEXT: sw a3, 12(sp)
+; RV32-NEXT: sw a2, 8(sp)
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vmul.vv v8, v8, v16
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vmul_xx_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
+; RV64-NEXT: vmv.v.x v8, a0
+; RV64-NEXT: vmul.vx v8, v8, a1
+; RV64-NEXT: ret
+ %head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
+ %splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
+ %head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
+ %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
+ %v = mul <vscale x 8 x i64> %splat1, %splat2
+ ret <vscale x 8 x i64> %v
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
index 81316f36170d2..57b558a77528c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
@@ -1144,3 +1144,33 @@ define <vscale x 8 x i64> @vor_vx_nxv8i64_3(<vscale x 8 x i64> %va) {
%vc = or <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i64> %vc
}
+
+define <vscale x 8 x i64> @vor_xx_nxv8i64(i64 %a, i64 %b) nounwind {
+; RV32-LABEL: vor_xx_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV32-NEXT: vlse64.v v8, (a0), zero
+; RV32-NEXT: sw a3, 12(sp)
+; RV32-NEXT: sw a2, 8(sp)
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vor.vv v8, v8, v16
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vor_xx_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
+; RV64-NEXT: vmv.v.x v8, a0
+; RV64-NEXT: vor.vx v8, v8, a1
+; RV64-NEXT: ret
+ %head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
+ %splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
+ %head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
+ %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
+ %v = or <vscale x 8 x i64> %splat1, %splat2
+ ret <vscale x 8 x i64> %v
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
index d4508047e51b8..450605560ec96 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
@@ -839,3 +839,32 @@ define <vscale x 8 x i64> @vsub_vx_nxv8i64_0(<vscale x 8 x i64> %va) {
ret <vscale x 8 x i64> %vc
}
+define <vscale x 8 x i64> @vsub_xx_nxv8i64(i64 %a, i64 %b) nounwind {
+; RV32-LABEL: vsub_xx_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV32-NEXT: vlse64.v v8, (a0), zero
+; RV32-NEXT: sw a3, 12(sp)
+; RV32-NEXT: sw a2, 8(sp)
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vsub.vv v8, v8, v16
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vsub_xx_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
+; RV64-NEXT: vmv.v.x v8, a0
+; RV64-NEXT: vsub.vx v8, v8, a1
+; RV64-NEXT: ret
+ %head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
+ %splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
+ %head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
+ %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
+ %v = sub <vscale x 8 x i64> %splat1, %splat2
+ ret <vscale x 8 x i64> %v
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
index e11caa6721b22..e8214569bcb40 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
@@ -1352,3 +1352,32 @@ define <vscale x 8 x i64> @vxor_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
ret <vscale x 8 x i64> %vc
}
+define <vscale x 8 x i64> @vxor_xx_nxv8i64(i64 %a, i64 %b) nounwind {
+; RV32-LABEL: vxor_xx_nxv8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV32-NEXT: vlse64.v v8, (a0), zero
+; RV32-NEXT: sw a3, 12(sp)
+; RV32-NEXT: sw a2, 8(sp)
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vxor.vv v8, v8, v16
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vxor_xx_nxv8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
+; RV64-NEXT: vmv.v.x v8, a0
+; RV64-NEXT: vxor.vx v8, v8, a1
+; RV64-NEXT: ret
+ %head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
+ %splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
+ %head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
+ %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
+ %v = xor <vscale x 8 x i64> %splat1, %splat2
+ ret <vscale x 8 x i64> %v
+}
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