[PATCH] D130010: [AArch64][SVE] Add ISel pattern to lower DUPLANE128 to LD1RQD

[Matt Devereau via Phabricator via llvm-commits]

MattDevereau created this revision.
MattDevereau added reviewers: paulwalker-arm, peterwaller-arm, bsmith, c-rhodes.
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Following on from https://reviews.llvm.org/D128902, lower DUPLANE128 to LD1RQD for integer load types from instruction selection.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D130010

Files:
  llvm/include/llvm/Target/TargetSelectionDAG.td
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
  llvm/test/CodeGen/AArch64/sve-ld1r.ll

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