[PATCH] D129980: [RISCV] Optimize (seteq (i64 (and X, 0xffffffff)), C1)
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Jul 17 20:20:49 PDT 2022
craig.topper created this revision.
craig.topper added reviewers: asb, luismarques, reames.
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(and X, 0xffffffff) requires 2 shifts in the base ISA. Since we
know the result is being used by a compare, we can use a sext_inreg
instead of an AND if we also modify C1 <https://reviews.llvm.org/C1> to have 33 sign bits instead
of 32 leading zeros.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D129980
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/i64-icmp.ll
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