[PATCH] D129757: [RISCV] Optimize SELECT_CC when condition is eq and the true value of select is zero

[Liao Chunyu via Phabricator via llvm-commits]

liaolucy updated this revision to Diff 445320.
liaolucy added a comment.

1. address craig.topper's comments, remove condition code check.

2. Also remove ConstantSDNode->isZero().


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129757/new/

https://reviews.llvm.org/D129757

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/double-convert-strict.ll
  llvm/test/CodeGen/RISCV/double-convert.ll
  llvm/test/CodeGen/RISCV/float-convert-strict.ll
  llvm/test/CodeGen/RISCV/float-convert.ll
  llvm/test/CodeGen/RISCV/fpclamptosat.ll
  llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll
  llvm/test/CodeGen/RISCV/half-convert-strict.ll
  llvm/test/CodeGen/RISCV/half-convert.ll
  llvm/test/CodeGen/RISCV/rv32zbb-zbp-zbkb.ll
  llvm/test/CodeGen/RISCV/rv32zbs.ll
  llvm/test/CodeGen/RISCV/rv64zbb.ll
  llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
  llvm/test/CodeGen/RISCV/uadd_sat.ll
  llvm/test/CodeGen/RISCV/uadd_sat_plus.ll
  llvm/test/CodeGen/RISCV/usub_sat.ll
  llvm/test/CodeGen/RISCV/usub_sat_plus.ll

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