[PATCH] D129757: [RISCV] Optimize SELECT_CC when condition is eq and the true value of select is zero

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:3894
     SDValue TargetCC = DAG.getCondCode(CCVal);
+    if (isa<ConstantSDNode>(TrueV) && CCVal == ISD::SETEQ) {
+      auto *ConstNode = cast<ConstantSDNode>(TrueV);
----------------
craig.topper wrote:
> This transform is equally valid to turn SETNE into SETEQ right?
This is valid for any condition code isn't it? We just need to invert the condition code.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D129757/new/

https://reviews.llvm.org/D129757