[PATCH] D129933: [DAG] SimplifyDemandedBits - relax "xor (X >> ShiftC), XorC --> (not X) >> ShiftC" to match only demanded bits

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll:81
   ret i32 %retval
 }
 
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I don't think this will appear in DAG, and Instcombine will fold this to a xor-shift-mask pattern: https://gcc.godbolt.org/z/nMdqeaGYh


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D129933/new/

https://reviews.llvm.org/D129933