[PATCH] D123496: [RISCV] Add Stackmap/Statepoint/Patchpoint support without targets

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp:101
+  SM.recordStackMap(*MILabel, MI);
+  assert(NumNOPBytes % 4 == 0 && "Invalid number of NOP bytes requested!");
+
----------------
Is it still invalid with RVC? You can have 2-byte NOPs there...


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Comment at: llvm/test/CodeGen/RISCV/rv64-patchpoint.ll:3
+; RUN: llc -mtriple=riscv64 -debug-entry-values -enable-misched=0                             < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -debug-entry-values -enable-misched=0 -fast-isel -fast-isel-abort=1 < %s | FileCheck %s
+
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RISCV doesn't have FastISel support, it is identical to the previous line


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Comment at: llvm/test/CodeGen/RISCV/rv64-stackmap.ll:1
+; RUN: llc -mtriple=riscv64                             < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -fast-isel -fast-isel-abort=1 < %s | FileCheck %s
----------------
Don't line up despite your attempts to make them


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Comment at: llvm/test/CodeGen/RISCV/stackmap-frame-setup.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -o - -verify-machineinstrs -mtriple=riscv64 -stop-after machine-sink %s | FileCheck %s --check-prefix=ISEL
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You've got no CHECK lines because this is outputting MIR not assembly, hence you want update_mir_test_checks.py


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Comment at: llvm/test/CodeGen/RISCV/stackmap-frame-setup.ll:16-18
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; FAST-ISEL: {{.*}}
+; ISEL: {{.*}}
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Huh?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123496/new/

https://reviews.llvm.org/D123496