[PATCH] D129888: [RISCV] Teach RISCVCodeGenPrepare to optimize (i64 (and (zext/sext (i32 X), C1)))

[Craig Topper via Phabricator via llvm-commits]

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If X is known positive by a dominating condition, we can fill in
ones into the upper bits of C1 <https://reviews.llvm.org/C1> if that would allow it to become an
simm12 allowing the use of ANDI.

This pattern often occurs in unrolled loops where the induction
variable has been widened.

To get the best benefit from this, I had to move the pass above
ConstantHoisting which is in addIRPasses. Otherwise the AND constant
is often hoisted away from the AND.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D129888

Files:
  llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/O3-pipeline.ll
  llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll
  llvm/test/CodeGen/RISCV/riscv-codegenprepare.ll

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