[llvm] bc0d656 - [RISCV] Fix mistake in RISCVTTIImpl::getIntImmCostInst.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-07-14T16:42:35-07:00
New Revision: bc0d656558cfa0cf29aa4889ac807570b1e9dfd1

URL: https://github.com/llvm/llvm-project/commit/bc0d656558cfa0cf29aa4889ac807570b1e9dfd1
DIFF: https://github.com/llvm/llvm-project/commit/bc0d656558cfa0cf29aa4889ac807570b1e9dfd1.diff

LOG: [RISCV] Fix mistake in RISCVTTIImpl::getIntImmCostInst.

zext.w requires Zba not Zbb. The test was also wrong, but had the
correct comment.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
    llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 29d3c5e491de..cb0947c5c39b 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -65,7 +65,7 @@ InstructionCost RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
     if (Imm == UINT64_C(0xffff) && ST->hasStdExtZbb())
       return TTI::TCC_Free;
     // zext.w
-    if (Imm == UINT64_C(0xffffffff) && ST->hasStdExtZbb())
+    if (Imm == UINT64_C(0xffffffff) && ST->hasStdExtZba())
       return TTI::TCC_Free;
     LLVM_FALLTHROUGH;
   case Instruction::Add:

diff  --git a/llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll b/llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll
index c6394685b127..92441afa9401 100644
--- a/llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll
+++ b/llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll
@@ -65,7 +65,7 @@ define i64 @test7(i64 %a) nounwind {
 }
 
 ; Check that we don't hoist zext.w with Zba.
-define i64 @test8(i64 %a) nounwind "target-features"="+zbb" {
+define i64 @test8(i64 %a) nounwind "target-features"="+zba" {
 ; CHECK-LABEL: test8
 ; CHECK: and i64 %a, 4294967295
   %1 = and i64 %a, 4294967295