[llvm] 65abc3a - [AMDGPU] Fix for the test failure caused by the 2e29b0138ca243c7d288622524a004c84acbbb9e
Alexander Timofeev via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 14 16:38:35 PDT 2022
Author: Alexander Timofeev
Date: 2022-07-15T01:38:03+02:00
New Revision: 65abc3a869bf67984b4d393afa2fb16b1690e70d
URL: https://github.com/llvm/llvm-project/commit/65abc3a869bf67984b4d393afa2fb16b1690e70d
DIFF: https://github.com/llvm/llvm-project/commit/65abc3a869bf67984b4d393afa2fb16b1690e70d.diff
LOG: [AMDGPU] Fix for the test failure caused by the 2e29b0138ca243c7d288622524a004c84acbbb9e
Fixing the idiv-licm.ll test failure
Differential Revision: https://reviews.llvm.org/D129819
Added:
Modified:
llvm/test/CodeGen/AMDGPU/idiv-licm.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/idiv-licm.ll b/llvm/test/CodeGen/AMDGPU/idiv-licm.ll
index a93492e14bf4..1c1332a53b59 100644
--- a/llvm/test/CodeGen/AMDGPU/idiv-licm.ll
+++ b/llvm/test/CodeGen/AMDGPU/idiv-licm.ll
@@ -105,6 +105,7 @@ define amdgpu_kernel void @udiv32_invariant_denom(i32 addrspace(1)* nocapture %a
; GFX11-NEXT: s_load_b32 s4, s[0:1], 0x2c
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
; GFX11-NEXT: s_mov_b64 s[2:3], 0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s4
; GFX11-NEXT: s_sub_i32 s5, 0, s4
@@ -113,36 +114,38 @@ define amdgpu_kernel void @udiv32_invariant_denom(i32 addrspace(1)* nocapture %a
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_lo_u32 v1, s5, v0
-; GFX11-NEXT: v_mul_hi_u32 v1, v0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, v0, v1
; GFX11-NEXT: .p2align 6
; GFX11-NEXT: .LBB0_1: ; %bb3
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_lo_u32 v2, s3, v0
-; GFX11-NEXT: v_mul_hi_u32 v3, s2, v0
-; GFX11-NEXT: v_add_nc_u32_e32 v2, v3, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_not_b32_e32 v3, v2
-; GFX11-NEXT: v_mul_lo_u32 v4, s5, v2
-; GFX11-NEXT: v_mul_lo_u32 v3, s4, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_nc_u32_e32 v4, s2, v4
-; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, s4, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_nc_u32_e32 v3, s2, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_readfirstlane_b32 s6, v0
+; GFX11-NEXT: s_mul_i32 s7, s5, s6
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_mul_hi_u32 s7, s6, s7
+; GFX11-NEXT: s_add_i32 s6, s6, s7
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_mul_i32 s7, s3, s6
+; GFX11-NEXT: s_mul_hi_u32 s6, s2, s6
+; GFX11-NEXT: s_add_i32 s6, s6, s7
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_mul_i32 s7, s5, s6
+; GFX11-NEXT: s_add_i32 s7, s2, s7
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cmp_ge_u32 s7, s4
+; GFX11-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX11-NEXT: s_add_i32 s8, s6, 1
+; GFX11-NEXT: s_not_b32 s9, s6
+; GFX11-NEXT: v_mov_b32_e32 v2, s8
+; GFX11-NEXT: s_mul_i32 s8, s4, s9
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_add_i32 s8, s2, s8
; GFX11-NEXT: s_add_u32 s2, s2, 1
+; GFX11-NEXT: v_mov_b32_e32 v3, s8
+; GFX11-NEXT: v_cndmask_b32_e32 v2, s6, v2, vcc_lo
; GFX11-NEXT: s_addc_u32 s3, s3, 0
-; GFX11-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
-; GFX11-NEXT: v_add_nc_u32_e32 v5, 1, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
+; GFX11-NEXT: v_dual_cndmask_b32 v3, s7, v3 :: v_dual_add_nc_u32 v4, 1, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, s4, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 1, v2
; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX11-NEXT: global_store_b32 v1, v2, s[0:1]
; GFX11-NEXT: s_add_u32 s0, s0, 4
@@ -261,6 +264,7 @@ define amdgpu_kernel void @urem32_invariant_denom(i32 addrspace(1)* nocapture %a
; GFX11-NEXT: s_load_b32 s4, s[0:1], 0x2c
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
; GFX11-NEXT: s_mov_b64 s[2:3], 0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s4
; GFX11-NEXT: s_sub_i32 s5, 0, s4
@@ -269,34 +273,34 @@ define amdgpu_kernel void @urem32_invariant_denom(i32 addrspace(1)* nocapture %a
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_lo_u32 v1, s5, v0
-; GFX11-NEXT: v_mul_hi_u32 v1, v0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, v0, v1
; GFX11-NEXT: .p2align 6
; GFX11-NEXT: .LBB1_1: ; %bb3
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_lo_u32 v2, s3, v0
-; GFX11-NEXT: v_mul_hi_u32 v3, s2, v0
-; GFX11-NEXT: v_add_nc_u32_e32 v2, v3, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_not_b32_e32 v3, v2
-; GFX11-NEXT: v_mul_lo_u32 v2, s5, v2
-; GFX11-NEXT: v_mul_lo_u32 v3, s4, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_add_nc_u32_e32 v2, s2, v2
-; GFX11-NEXT: v_add_nc_u32_e32 v3, s2, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, s4, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_readfirstlane_b32 s6, v0
+; GFX11-NEXT: s_mul_i32 s7, s5, s6
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_mul_hi_u32 s7, s6, s7
+; GFX11-NEXT: s_add_i32 s6, s6, s7
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_mul_i32 s7, s3, s6
+; GFX11-NEXT: s_mul_hi_u32 s6, s2, s6
+; GFX11-NEXT: s_add_i32 s6, s6, s7
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_not_b32 s7, s6
+; GFX11-NEXT: s_mul_i32 s6, s5, s6
+; GFX11-NEXT: s_mul_i32 s7, s4, s7
+; GFX11-NEXT: s_add_i32 s6, s2, s6
+; GFX11-NEXT: s_add_i32 s7, s2, s7
+; GFX11-NEXT: s_cmp_ge_u32 s6, s4
+; GFX11-NEXT: s_cselect_b32 s6, s7, s6
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_sub_i32 s7, s6, s4
+; GFX11-NEXT: s_cmp_ge_u32 s6, s4
+; GFX11-NEXT: s_cselect_b32 s6, s7, s6
; GFX11-NEXT: s_add_u32 s2, s2, 1
+; GFX11-NEXT: v_mov_b32_e32 v2, s6
; GFX11-NEXT: s_addc_u32 s3, s3, 0
-; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_subrev_nc_u32_e32 v3, s4, v2
-; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, s4, v2
-; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX11-NEXT: global_store_b32 v1, v2, s[0:1]
; GFX11-NEXT: s_add_u32 s0, s0, 4
; GFX11-NEXT: s_addc_u32 s1, s1, 0
@@ -418,6 +422,8 @@ define amdgpu_kernel void @sdiv32_invariant_denom(i32 addrspace(1)* nocapture %a
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b32 s3, s[0:1], 0x2c
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
+; GFX11-NEXT: s_mov_b32 s4, 0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_ashr_i32 s2, s3, 31
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
@@ -425,35 +431,39 @@ define amdgpu_kernel void @sdiv32_invariant_denom(i32 addrspace(1)* nocapture %a
; GFX11-NEXT: s_xor_b32 s3, s3, s2
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s3
-; GFX11-NEXT: s_sub_i32 s4, 0, s3
+; GFX11-NEXT: s_sub_i32 s5, 0, s3
; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX11-NEXT: v_mul_lo_u32 v1, s4, v0
-; GFX11-NEXT: s_mov_b32 s4, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_hi_u32 v1, v0, v1
-; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, v0, v1
; GFX11-NEXT: .p2align 6
; GFX11-NEXT: .LBB2_1: ; %bb3
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_hi_u32 v2, s4, v0
-; GFX11-NEXT: v_mul_lo_u32 v3, v2, s3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_sub_nc_u32_e32 v3, s4, v3
+; GFX11-NEXT: v_readfirstlane_b32 s6, v0
+; GFX11-NEXT: s_mul_i32 s7, s5, s6
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_mul_hi_u32 s7, s6, s7
+; GFX11-NEXT: s_add_i32 s6, s6, s7
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_mul_hi_u32 s6, s4, s6
+; GFX11-NEXT: s_mul_i32 s7, s6, s3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_sub_i32 s7, s4, s7
+; GFX11-NEXT: s_cmp_ge_u32 s7, s3
+; GFX11-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX11-NEXT: s_add_i32 s8, s6, 1
; GFX11-NEXT: s_add_i32 s4, s4, 1
-; GFX11-NEXT: v_subrev_nc_u32_e32 v5, s3, v3
+; GFX11-NEXT: v_mov_b32_e32 v2, s8
+; GFX11-NEXT: s_sub_i32 s8, s7, s3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_mov_b32_e32 v3, s8
+; GFX11-NEXT: v_cndmask_b32_e32 v2, s6, v2, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_cndmask_b32 v3, s7, v3 :: v_dual_add_nc_u32 v4, 1, v2
; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, s3, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_cndmask_b32 v3, v3, v5 :: v_dual_add_nc_u32 v4, 1, v2
-; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, s3, v3
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 1, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX11-NEXT: v_xor_b32_e32 v2, s2, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -570,41 +580,43 @@ define amdgpu_kernel void @srem32_invariant_denom(i32 addrspace(1)* nocapture %a
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_ashr_i32 s3, s2, 31
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s2, s2, s3
; GFX11-NEXT: s_xor_b32 s2, s2, s3
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_mov_b32 s3, 0
; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX11-NEXT: s_sub_i32 s3, 0, s2
+; GFX11-NEXT: s_sub_i32 s4, 0, s2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX11-NEXT: v_mul_lo_u32 v1, s3, v0
-; GFX11-NEXT: s_mov_b32 s3, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_hi_u32 v1, v0, v1
-; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, v0, v1
; GFX11-NEXT: .p2align 6
; GFX11-NEXT: .LBB3_1: ; %bb3
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_hi_u32 v2, s3, v0
-; GFX11-NEXT: v_mul_lo_u32 v2, v2, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_sub_nc_u32_e32 v2, s3, v2
+; GFX11-NEXT: v_readfirstlane_b32 s5, v0
+; GFX11-NEXT: s_mul_i32 s6, s4, s5
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_mul_hi_u32 s6, s5, s6
+; GFX11-NEXT: s_add_i32 s5, s5, s6
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_mul_hi_u32 s5, s3, s5
+; GFX11-NEXT: s_mul_i32 s5, s5, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_sub_i32 s5, s3, s5
+; GFX11-NEXT: s_sub_i32 s6, s5, s2
+; GFX11-NEXT: s_cmp_ge_u32 s5, s2
+; GFX11-NEXT: s_cselect_b32 s5, s6, s5
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_sub_i32 s6, s5, s2
+; GFX11-NEXT: s_cmp_ge_u32 s5, s2
+; GFX11-NEXT: s_cselect_b32 s5, s6, s5
; GFX11-NEXT: s_add_i32 s3, s3, 1
-; GFX11-NEXT: v_subrev_nc_u32_e32 v3, s2, v2
-; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
-; GFX11-NEXT: v_subrev_nc_u32_e32 v3, s2, v2
-; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX11-NEXT: v_mov_b32_e32 v2, s5
; GFX11-NEXT: global_store_b32 v1, v2, s[0:1]
; GFX11-NEXT: s_add_u32 s0, s0, 4
; GFX11-NEXT: s_addc_u32 s1, s1, 0
@@ -704,35 +716,37 @@ define amdgpu_kernel void @udiv16_invariant_denom(i16 addrspace(1)* nocapture %a
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b32 s4, s[0:1], 0x2c
; GFX11-NEXT: s_load_b64 s[2:3], s[0:1], 0x24
-; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 0
+; GFX11-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-NEXT: s_mov_b32 s1, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_and_b32 s0, 0xffff, s4
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cvt_f32_u32_e32 v2, s0
-; GFX11-NEXT: v_rcp_iflag_f32_e32 v3, v2
+; GFX11-NEXT: s_mov_b32 s4, 0
+; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_rcp_iflag_f32_e32 v1, v0
; GFX11-NEXT: .p2align 6
; GFX11-NEXT: .LBB4_1: ; %bb3
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v4
-; GFX11-NEXT: v_add_nc_u16 v4, v4, 1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cvt_f32_u32_e32 v7, v0
-; GFX11-NEXT: v_lshlrev_b64 v[5:6], 1, v[0:1]
-; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x400, v4
+; GFX11-NEXT: s_and_b32 s0, 0xffff, s4
+; GFX11-NEXT: v_add_nc_u16 v3, s4, 1
+; GFX11-NEXT: v_cvt_f32_u32_e32 v4, s0
+; GFX11-NEXT: s_lshl_b64 s[4:5], s[0:1], 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_add_u32 s6, s2, s4
+; GFX11-NEXT: v_readfirstlane_b32 s4, v3
+; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x400, v3
; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_mul_f32_e32 v0, v7, v3
-; GFX11-NEXT: v_add_co_u32 v5, s0, s2, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
-; GFX11-NEXT: v_trunc_f32_e32 v0, v0
+; GFX11-NEXT: v_mul_f32_e32 v3, v4, v1
+; GFX11-NEXT: s_addc_u32 s7, s3, s5
; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_fma_f32 v7, -v0, v2, v7
-; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX11-NEXT: v_cmp_ge_f32_e64 s0, |v7|, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_add_co_ci_u32_e64 v0, s0, 0, v0, s0
-; GFX11-NEXT: global_store_b16 v[5:6], v0, off
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_trunc_f32_e32 v3, v3
+; GFX11-NEXT: v_fma_f32 v4, -v3, v0, v4
+; GFX11-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_ge_f32_e64 s0, |v4|, v0
+; GFX11-NEXT: v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
+; GFX11-NEXT: global_store_b16 v2, v3, s[6:7]
; GFX11-NEXT: s_cbranch_vccz .LBB4_1
; GFX11-NEXT: ; %bb.2: ; %bb2
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
@@ -962,48 +976,47 @@ define amdgpu_kernel void @sdiv16_invariant_denom(i16 addrspace(1)* nocapture %a
; GFX11-LABEL: sdiv16_invariant_denom:
; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s4, s[0:1], 0x2c
-; GFX11-NEXT: s_load_b64 s[2:3], s[0:1], 0x24
-; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 0
+; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
+; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
+; GFX11-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-NEXT: s_mov_b32 s3, 0
+; GFX11-NEXT: s_mov_b32 s5, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_sext_i32_i16 s4, s4
+; GFX11-NEXT: s_sext_i32_i16 s4, s2
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cvt_f32_i32_e32 v2, s4
-; GFX11-NEXT: v_rcp_iflag_f32_e32 v3, v2
-; GFX11-NEXT: s_set_inst_prefetch_distance 0x1
+; GFX11-NEXT: v_cvt_f32_i32_e32 v0, s4
+; GFX11-NEXT: v_rcp_iflag_f32_e32 v1, v0
; GFX11-NEXT: .p2align 6
; GFX11-NEXT: .LBB6_1: ; %bb3
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX11-NEXT: v_bfe_i32 v5, v4, 0, 16
-; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v4
-; GFX11-NEXT: v_add_nc_u16 v4, v4, 1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_cvt_f32_i32_e32 v7, v5
-; GFX11-NEXT: v_xor_b32_e32 v8, s4, v5
-; GFX11-NEXT: v_lshlrev_b64 v[5:6], 1, v[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x400, v4
-; GFX11-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_mul_f32_e32 v0, v7, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_ashrrev_i32_e32 v8, 30, v8
-; GFX11-NEXT: v_add_co_u32 v5, s0, s2, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_trunc_f32_e32 v0, v0
-; GFX11-NEXT: v_or_b32_e32 v8, 1, v8
-; GFX11-NEXT: v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
-; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_fma_f32 v7, -v0, v2, v7
-; GFX11-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX11-NEXT: v_cmp_ge_f32_e64 s1, |v7|, |v2|
+; GFX11-NEXT: s_sext_i32_i16 s2, s5
+; GFX11-NEXT: v_add_nc_u16 v3, s5, 1
+; GFX11-NEXT: v_cvt_f32_i32_e32 v4, s2
+; GFX11-NEXT: s_xor_b32 s2, s2, s4
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_ashr_i32 s2, s2, 30
+; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x400, v3
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v1
+; GFX11-NEXT: s_or_b32 s2, s2, 1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v7, 0, v8, s1
-; GFX11-NEXT: v_add_nc_u32_e32 v0, v0, v7
-; GFX11-NEXT: global_store_b16 v[5:6], v0, off
+; GFX11-NEXT: v_trunc_f32_e32 v5, v5
+; GFX11-NEXT: v_fma_f32 v4, -v5, v0, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cmp_ge_f32_e64 s6, |v4|, |v0|
+; GFX11-NEXT: v_cvt_i32_f32_e32 v4, v5
+; GFX11-NEXT: s_and_b32 s6, s6, exec_lo
+; GFX11-NEXT: s_cselect_b32 s6, s2, 0
+; GFX11-NEXT: s_and_b32 s2, s5, 0xffff
+; GFX11-NEXT: v_readfirstlane_b32 s5, v3
+; GFX11-NEXT: v_add_nc_u32_e32 v3, s6, v4
+; GFX11-NEXT: s_lshl_b64 s[6:7], s[2:3], 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_add_u32 s6, s0, s6
+; GFX11-NEXT: s_addc_u32 s7, s1, s7
+; GFX11-NEXT: global_store_b16 v2, v3, s[6:7]
; GFX11-NEXT: s_cbranch_vccz .LBB6_1
; GFX11-NEXT: ; %bb.2: ; %bb2
-; GFX11-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-NEXT: s_endpgm
bb:
@@ -1109,46 +1122,49 @@ define amdgpu_kernel void @srem16_invariant_denom(i16 addrspace(1)* nocapture %a
; GFX11-LABEL: srem16_invariant_denom:
; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s4, s[0:1], 0x2c
-; GFX11-NEXT: s_load_b64 s[2:3], s[0:1], 0x24
-; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 0
+; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
+; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
+; GFX11-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-NEXT: s_mov_b32 s3, 0
+; GFX11-NEXT: s_mov_b32 s5, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_sext_i32_i16 s1, s4
+; GFX11-NEXT: s_sext_i32_i16 s4, s2
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cvt_f32_i32_e32 v2, s1
-; GFX11-NEXT: v_rcp_iflag_f32_e32 v3, v2
+; GFX11-NEXT: v_cvt_f32_i32_e32 v0, s4
+; GFX11-NEXT: v_rcp_iflag_f32_e32 v1, v0
; GFX11-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-NEXT: .p2align 6
; GFX11-NEXT: .LBB7_1: ; %bb3
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX11-NEXT: v_bfe_i32 v7, v4, 0, 16
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cvt_f32_i32_e32 v5, v7
-; GFX11-NEXT: v_xor_b32_e32 v6, s1, v7
+; GFX11-NEXT: s_sext_i32_i16 s8, s5
+; GFX11-NEXT: v_add_nc_u16 v3, s5, 1
+; GFX11-NEXT: v_cvt_f32_i32_e32 v4, s8
+; GFX11-NEXT: s_xor_b32 s2, s8, s4
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_ashr_i32 s2, s2, 30
+; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x400, v3
; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_mul_f32_e32 v8, v5, v3
-; GFX11-NEXT: v_ashrrev_i32_e32 v6, 30, v6
-; GFX11-NEXT: v_trunc_f32_e32 v8, v8
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v6, 1, v6
-; GFX11-NEXT: v_fma_f32 v5, -v8, v2, v5
-; GFX11-NEXT: v_cvt_i32_f32_e32 v8, v8
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cmp_ge_f32_e64 vcc_lo, |v5|, |v2|
-; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v4
-; GFX11-NEXT: v_add_nc_u16 v4, v4, 1
-; GFX11-NEXT: v_cndmask_b32_e32 v9, 0, v6, vcc_lo
-; GFX11-NEXT: v_lshlrev_b64 v[5:6], 1, v[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x400, v4
-; GFX11-NEXT: v_add_nc_u32_e32 v0, v8, v9
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_co_u32 v5, s0, s2, v5
-; GFX11-NEXT: v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_lo_u32 v0, v0, s1
-; GFX11-NEXT: v_sub_nc_u32_e32 v0, v7, v0
-; GFX11-NEXT: global_store_b16 v[5:6], v0, off
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v1
+; GFX11-NEXT: s_or_b32 s2, s2, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_trunc_f32_e32 v5, v5
+; GFX11-NEXT: v_fma_f32 v4, -v5, v0, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cmp_ge_f32_e64 s6, |v4|, |v0|
+; GFX11-NEXT: v_cvt_i32_f32_e32 v4, v5
+; GFX11-NEXT: s_and_b32 s6, s6, exec_lo
+; GFX11-NEXT: s_cselect_b32 s6, s2, 0
+; GFX11-NEXT: s_and_b32 s2, s5, 0xffff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_add_nc_u32_e32 v4, s6, v4
+; GFX11-NEXT: v_readfirstlane_b32 s5, v3
+; GFX11-NEXT: s_lshl_b64 s[6:7], s[2:3], 1
+; GFX11-NEXT: s_add_u32 s6, s0, s6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_lo_u32 v3, v4, s4
+; GFX11-NEXT: s_addc_u32 s7, s1, s7
+; GFX11-NEXT: v_sub_nc_u32_e32 v3, s8, v3
+; GFX11-NEXT: global_store_b16 v2, v3, s[6:7]
; GFX11-NEXT: s_cbranch_vccz .LBB7_1
; GFX11-NEXT: ; %bb.2: ; %bb2
; GFX11-NEXT: s_set_inst_prefetch_distance 0x2
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