[PATCH] D129291: [NVPTX] Promote i24, i40, i48 and i56 to next power-of-two register when passing

[Artem Belevich via Phabricator via llvm-commits]

tra added inline comments.


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Comment at: llvm/test/CodeGen/NVPTX/param-load-store.ll:559-562
+; CHECK:      ld.param.u8     [[E8:%r[0-9]+]], [test_i23_param_0+2];
+; CHECK:      shl.b32         [[S16:%r[0-9]+]], [[E8]], 16;
+; CHECK:      ld.param.u16    [[E16:%r[0-9]+]], [test_i23_param_0];
+; CHECK:      or.b32          [[E32:%r[0-9]+]], [[E16]], [[S16]];
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This, and other tests dealing with multiple loads/stores of parts of the argument may be fragile. First, the order of loads would not necessarily be guaranteed. Second -- the way LLVM reconstructs the value from parts may also change.

I would stick with a set of `CHECK-DAG: ld.param.XX {{.*}} [test_i23_param_0+Y]`. All we care about here is that we load the right set of bits. We can assume that reconstructing the integer is handled by appropriate tests already.



CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129291/new/

https://reviews.llvm.org/D129291