[PATCH] D128582: Enable SeparateConstOffsetFromGEPPass() at -O3 and -O2
Shubham Narlawar via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 14 11:57:42 PDT 2022
gsocshubham updated this revision to Diff 444754.
gsocshubham added a comment.
Move GEP pass before LSR pass.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D128582/new/
https://reviews.llvm.org/D128582
Files:
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
Index: llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -563,17 +563,6 @@
addPass(createFalkorMarkStridedAccessesPass());
}
- TargetPassConfig::addIRPasses();
-
- addPass(createAArch64StackTaggingPass(
- /*IsOptNone=*/TM->getOptLevel() == CodeGenOpt::None));
-
- // Match interleaved memory accesses to ldN/stN intrinsics.
- if (TM->getOptLevel() != CodeGenOpt::None) {
- addPass(createInterleavedLoadCombinePass());
- addPass(createInterleavedAccessPass());
- }
-
if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
// Call SeparateConstOffsetFromGEP pass to extract constants within indices
// and lower a GEP with multiple indices to either arithmetic operations or
@@ -587,6 +576,17 @@
addPass(createLICMPass());
}
+ TargetPassConfig::addIRPasses();
+
+ addPass(createAArch64StackTaggingPass(
+ /*IsOptNone=*/TM->getOptLevel() == CodeGenOpt::None));
+
+ // Match interleaved memory accesses to ldN/stN intrinsics.
+ if (TM->getOptLevel() != CodeGenOpt::None) {
+ addPass(createInterleavedLoadCombinePass());
+ addPass(createInterleavedAccessPass());
+ }
+
// Add Control Flow Guard checks.
if (TM->getTargetTriple().isOSWindows())
addPass(createCFGuardCheckPass());
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