[llvm] c0df6bc - [RISCV][LSR] Add coverage for ICmpZero with scaled vscale values
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 14 10:56:13 PDT 2022
Author: Philip Reames
Date: 2022-07-14T10:55:31-07:00
New Revision: c0df6bc949afd79a340224a9e120f58451ebe10e
URL: https://github.com/llvm/llvm-project/commit/c0df6bc949afd79a340224a9e120f58451ebe10e
DIFF: https://github.com/llvm/llvm-project/commit/c0df6bc949afd79a340224a9e120f58451ebe10e.diff
LOG: [RISCV][LSR] Add coverage for ICmpZero with scaled vscale values
Follow up to 3bc09c7da5 - remove a fixme I forgot to remove, and add test cases showing remaining work.
Note that scaled vscales show up in vectorized code from a couple of sources:
* Element types smaller than vector block size (i.e. everything under i64)
* Unrolling
* LMUL > 1
The largest scaling we can currently have is 256 (e8 in every possible vector register). More practically useful scales are in the 2-16 range.
Added:
Modified:
llvm/test/Transforms/LoopStrengthReduce/RISCV/icmp-zero.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/LoopStrengthReduce/RISCV/icmp-zero.ll b/llvm/test/Transforms/LoopStrengthReduce/RISCV/icmp-zero.ll
index 58cc10c1e541f..72549ce650c0e 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/RISCV/icmp-zero.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/RISCV/icmp-zero.ll
@@ -153,7 +153,6 @@ exit:
ret void
}
-; FIXME: We can hoist this because vscale is never equal to zero
define void @icmp_zero_urem_vscale(i64 %N, ptr %p) {
; CHECK-LABEL: @icmp_zero_urem_vscale(
; CHECK-NEXT: entry:
@@ -185,4 +184,137 @@ exit:
ret void
}
+define void @icmp_zero_urem_vscale_mul8(i64 %N, ptr %p) {
+; CHECK-LABEL: @icmp_zero_urem_vscale_mul8(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i64 [[VSCALE]], 8
+; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[N:%.*]], [[MUL]]
+; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
+; CHECK: vector.body:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT: store i64 0, ptr [[P:%.*]], align 8
+; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 2
+; CHECK-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV_NEXT]], [[UREM]]
+; CHECK-NEXT: br i1 [[DONE]], label [[EXIT:%.*]], label [[VECTOR_BODY]]
+; CHECK: exit:
+; CHECK-NEXT: ret void
+;
+entry:
+ %vscale = call i64 @llvm.vscale.i64()
+ %mul = mul nuw nsw i64 %vscale, 8
+ %urem = urem i64 %N, %mul
+ br label %vector.body
+
+vector.body:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %vector.body ]
+ store i64 0, ptr %p
+ %iv.next = add i64 %iv, 2
+ %done = icmp eq i64 %iv.next, %urem
+ br i1 %done, label %exit, label %vector.body
+
+exit:
+ ret void
+}
+
+
+define void @icmp_zero_urem_vscale_mul64(i64 %N, ptr %p) {
+; CHECK-LABEL: @icmp_zero_urem_vscale_mul64(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i64 [[VSCALE]], 64
+; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[N:%.*]], [[MUL]]
+; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
+; CHECK: vector.body:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT: store i64 0, ptr [[P:%.*]], align 8
+; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 2
+; CHECK-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV_NEXT]], [[UREM]]
+; CHECK-NEXT: br i1 [[DONE]], label [[EXIT:%.*]], label [[VECTOR_BODY]]
+; CHECK: exit:
+; CHECK-NEXT: ret void
+;
+entry:
+ %vscale = call i64 @llvm.vscale.i64()
+ %mul = mul nuw nsw i64 %vscale, 64
+ %urem = urem i64 %N, %mul
+ br label %vector.body
+
+vector.body:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %vector.body ]
+ store i64 0, ptr %p
+ %iv.next = add i64 %iv, 2
+ %done = icmp eq i64 %iv.next, %urem
+ br i1 %done, label %exit, label %vector.body
+
+exit:
+ ret void
+}
+
+define void @icmp_zero_urem_vscale_shl3(i64 %N, ptr %p) {
+; CHECK-LABEL: @icmp_zero_urem_vscale_shl3(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[SHL:%.*]] = shl i64 [[VSCALE]], 3
+; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[N:%.*]], [[SHL]]
+; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
+; CHECK: vector.body:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT: store i64 0, ptr [[P:%.*]], align 8
+; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 2
+; CHECK-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV_NEXT]], [[UREM]]
+; CHECK-NEXT: br i1 [[DONE]], label [[EXIT:%.*]], label [[VECTOR_BODY]]
+; CHECK: exit:
+; CHECK-NEXT: ret void
+;
+entry:
+ %vscale = call i64 @llvm.vscale.i64()
+ %shl = shl i64 %vscale, 3
+ %urem = urem i64 %N, %shl
+ br label %vector.body
+
+vector.body:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %vector.body ]
+ store i64 0, ptr %p
+ %iv.next = add i64 %iv, 2
+ %done = icmp eq i64 %iv.next, %urem
+ br i1 %done, label %exit, label %vector.body
+
+exit:
+ ret void
+}
+
+define void @icmp_zero_urem_vscale_shl6(i64 %N, ptr %p) {
+; CHECK-LABEL: @icmp_zero_urem_vscale_shl6(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[SHL:%.*]] = shl i64 [[VSCALE]], 6
+; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[N:%.*]], [[SHL]]
+; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
+; CHECK: vector.body:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT: store i64 0, ptr [[P:%.*]], align 8
+; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 2
+; CHECK-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV_NEXT]], [[UREM]]
+; CHECK-NEXT: br i1 [[DONE]], label [[EXIT:%.*]], label [[VECTOR_BODY]]
+; CHECK: exit:
+; CHECK-NEXT: ret void
+;
+entry:
+ %vscale = call i64 @llvm.vscale.i64()
+ %shl = shl i64 %vscale, 6
+ %urem = urem i64 %N, %shl
+ br label %vector.body
+
+vector.body:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %vector.body ]
+ store i64 0, ptr %p
+ %iv.next = add i64 %iv, 2
+ %done = icmp eq i64 %iv.next, %urem
+ br i1 %done, label %exit, label %vector.body
+
+exit:
+ ret void
+}
+
declare i64 @llvm.vscale.i64()
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