[PATCH] D129735: [WIP][RISCV] Add new pass to transform undef to zero-init for vector values.

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added a comment.

I guess I might spend few more time to see the possibility to improve that.



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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vector-trunc-vp.ll:391
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmv.v.i v8, 0
 ; CHECK-NEXT:    vsetvli zero, a4, e32, m4, ta, mu
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Highlight a very bad impact here: The code gen really seems silly here when there is sequence of INSERT_SUBREG for building a vector...


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D129735/new/

https://reviews.llvm.org/D129735