[PATCH] D129735: [WIP][RISCV] Add new pass to transform undef to zero-init for vector values.

Thu Jul 14 08:47:15 PDT 2022

kito-cheng added a comment.

> Sorry, I've not had time to think about this today. Just wanted to check: does this pass actually fix the test I added in D129639 <https://reviews.llvm.org/D129639>? Because that isn't (obviously) using undef input values, at least in the IR.

Short answer is yes, but come with few more vmv.v.i instruction for prevent allocated same reg, `poison` and `undef` all turn into IMPLICIT_DEF in back-end.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129735/new/

https://reviews.llvm.org/D129735